Package com.xilinx.rapidwright.design

Interface Summary

Interface	Description
PBlockCorner	An attempt to hide the two different types of objects (Site and ClockRegion) from the view of the PBlockRange.

Class Summary

Class	Description
AbstractModuleInst<ModuleT,PlacementT,T extends AbstractModuleInst<ModuleT,PlacementT,T>>	Abstract base class for ModuleInst and ModuleImplsInst
AltPinMapping	An AltPinMapping is used on routethru cells when the routethru fans out to more than one sink.
BELAttr	Stores a BEL attribute with the associated net.
Cell	A cell corresponds to the leaf cell within the logical netlist EDIFCellInst and provides a mapping to a physical location BEL on the device.
CellPin
CellPinStaticDefaults	Helper class to provide default static (GND or VCC) connection values to newly created cells.
Design	The Design class is the central location that maintains the physical netlist and has hooks and references into the logical netlist.
DesignTools	A collection of methods to operate on Design objects.
DRC	Parent DRC that executes a list of child DRCs, returning the sum of all failed checks.
MetadataParser	Parses metadata file generated by the Tcl command in rapidwright.tcl/generate_metadata.
Module	Represents a collection of SiteInst and Net objects that can be instantiated as a ModuleInst.
ModuleCache	Allows RapidWright to read/write modules to a serialized, binary file.
ModuleImpls	A wrapper class for multiple implementations of a module.
ModuleImplsInst	A module instance with flexible implementation.
ModuleInst	There is no direct representation of a module instance in Vivado.
ModulePlacement	A placement of a ModuleImplsInst.
Net	This class represents the physical net to be routed (both inter-site and intra-site).
NetTools
NetTools.NodeTree
PartitionPin	Represents a routing interface point that can be attached to a logical port or pin of a cell.
PinSwap	Class specifically created to manage pin swaps on the same site (such as LUTs) Created on: Nov 22, 2017
Port	This class represents the ports used to define the interfaces of modules.
RelocatableTileRectangle	A TileRectangle that is relocatable.
RTLStubGenerator	Generates Verilog or VHDL stub files to instantiate design checkpoint files.
SimpleTileRectangle	A TileRectangle that uses Row/Column indices for storage.
SiteConfig	Represents a site and keeps tracks of attributes on its BELs.
SiteInst	This class represents the instance of a site as configured by the user design.
SitePinInst	This class represents the site pin sources and sinks in a physical net.
TileRectangle	A Rectangle of tiles, i.e.
VivadoProp	Captures unisim property values with associated Vivado types.

Enum Summary

Enum	Description
ConstraintGroup
NetType	This enum is simply a way to check net types easier than using Strings.
PinType
PortType	Created on: May 10, 2016
Unisim	Generated on: Sat Jun 07 20:43:57 MDT 2025 by: com.xilinx.rapidwright.release.UnisimParser Enumerates supported Unisim primitives that map to Xilinx devices.
VivadoPropType	Enumerates the Type of properties found when querying Vivado objects with report_property.