DesignTools

Object
- com.xilinx.rapidwright.design.DesignTools

```
public class DesignTools
extends Object
```
A collection of methods to operate on Design objects. Created on: Dec 7, 2015

Field Summary

Fields
Modifier and Type	Field and Description
`static Map<Series,Map<String,Pair<String,String>>>`	`belTypeSitePinNameMapping` Mapping from device Series to another mapping from FF BEL name to CKEN/SRST site pin name

Constructor Summary

Constructors
Constructor and Description

DesignTools()

Constructors
Constructor and Description
`DesignTools()`

Method Summary

All Methods Static Methods Concrete Methods
Modifier and Type	Method and Description
`static void`	`addProhibitConstraint(Design design, List<String> belLocations)` Adds a PROHIBIT constraint to the specified BEL Locations (ex: "SLICE_X10Y10/AFF")
`static boolean`	`areAllPinsConnectedToALUT(Net n)` Determines if all the pins connected to this net connect to only LUTs
`static void`	`batchRemoveSitePins(Map<Net,Set<SitePinInst>> deferredRemovals, boolean preserveOtherRoutes)` Remove a batch of site pins from nets for efficiency purposes.
`static Map<UtilizationType,Integer>`	`calculateUtilization(Collection<SiteInst> siteInsts)`
`static Map<UtilizationType,Integer>`	`calculateUtilization(Design d)`
`static Map<UtilizationType,Integer>`	`calculateUtilization(Design d, PBlock pblock)`
`static void`	`copyImplementation(Design src, Design dest, boolean copyStaticNets, boolean copyOnlyInternalNets, boolean lockPlacement, boolean lockRouting, Map<String,String> srcToDestInstNames)` Copies the logic and implementation of a set of cells from one design to another with additional flags to control copying nets.
`static void`	`copyImplementation(Design src, Design dest, boolean lockPlacement, boolean lockRouting, Map<String,String> srcToDestInstNames)` Copies the logic and implementation of a set of cells from one design to another.
`static void`	`copyImplementation(Design src, Design dest, boolean lockPlacement, boolean lockRouting, String... instNames)` Copies the logic and implementation of a set of cells from one design to another.
`static void`	`copyImplementation(Design src, Design dest, String... instNames)` Copies the logic and implementation of a set of cells from one design to another.
`static void`	`createA1A6ToStaticNets(Design design)`
`static void`	`createCeClkOfRoutethruFFToVCC(Design design)`
`static void`	`createCeSrRstPinsToVCC(Design design)` Create and add any missing SitePinInst-s belonging to the VCC net.
`static void`	`createMissingSitePinInsts(Design design)` Creates all missing SitePinInsts in a design, except GLOBAL_USEDNET.
`static List<SitePinInst>`	`createMissingSitePinInsts(Design design, Net net)` Creates any and all missing SitePinInsts for this net.
`static void`	`createMissingStaticSitePins(BELPin belPin, SiteInst si, Cell cell)`
`static ModuleImplsInst`	`createModuleImplsInst(Design design, String name, ModuleImpls module)` Create a `ModuleImplsInst`, i.e.
`static void`	`createModuleInstsFromModuleImplsInsts(Design design, Collection<ModuleImplsInst> instances, Collection<ImplsPath> paths)` In a design containing `ModuleImplsInst`s, convert them into `ModuleInst`s so that the design can be exported to a checkpoint
`static SitePinInst`	`createPinAndAddToNet(Cell cell, String cellPinName, Net net)` Creates a new pin on a site connected to the cell pin and also adds it to the provided net.
`static void`	`createPossiblePinsToStaticNets(Design design)`
`static List<PIP>`	`findRoutingPath(Node start, Node end)` Demonstrates a rudimentary path expansion for finding a routing path in the interconnect.
`static List<PIP>`	`findRoutingPath(RouteNode start, RouteNode end)` Demonstrates a rudimentary path expansion for finding a routing path in the interconnect.
`static void`	`fullyRemoveCell(Design design, Cell cell, Map<Net,Set<SitePinInst>> deferRemovals)` This method will completely remove a placed cell (both logical and physical) from a design.
`static void`	`fullyUnplaceCell(Cell cell, Map<Net,Set<SitePinInst>> deferRemovals)` This method will fully unplace (but not remove) a physical cell from a design.
`static Path`	`generateReadableEDIF(Path dcp, Path edfFileName)` Use Vivado to create a readable version of the EDIF file inside a design checkpoint.
`static Job`	`generateReadableEDIFJob(Path checkpoint, Path edif)` Create a Job running Vivado to create a readable version of the EDIF inside the checkpoint to a separate file.
`static List<String>`	`getAllRoutedSitePinsFromPhysicalPin(Cell cell, Net net, String belPinName)` Gets all site pins that are currently routed to the specified cell pin.
`static Net`	`getClockDomain(Design d, String edifNet)`
`static Set<BELPin>`	`getConnectedBELPins(BELPin pin, SiteInst si)` Looks in the site instance for BEL pins connected to this BEL pin and SiteInst.
`static Set<BELPin>`	`getConnectedBELPins(SitePinInst pin)` Looks in the site instance for BEL pins connected to this site pin.
`static Set<Cell>`	`getConnectedCells(BELPin pin, SiteInst si)` Looks in the site instance for cells connected to this BEL pin and SiteInst.
`static Set<Cell>`	`getConnectedCells(SitePinInst pin)` Looks in the site instance for cells connected to this site pin.
`static List<PIP>`	`getConnectionPIPs(SitePinInst sinkPin)` Finds the essential PIPs which connect the provided sink pin to its source.
`static ArrayList<BELPin>`	`getCorrespondingBELInputPins(BELPin outputPin, SiteInst inst)`
`static ArrayList<BELPin>`	`getCorrespondingBELOutputPins(BELPin inputPin, SiteInst inst)` TODO - Work in progress
`static BELPin`	`getCorrespondingRBELInputPin(BELPin outputPin, SiteInst inst)` Uses SitePIP information in the site instance to determine the driving input of the RBEL element output pin.
`static BELPin`	`getCorrespondingRBELOutputPin(BELPin inputPin, SiteInst inst)` Returns the element's output pin corresponding that is being driven by the provided input pin.
`static SiteInst`	`getCorrespondingSiteInst(Design design, SiteInst orig, Site newAnchor, Module module)` Gets or creates the corresponding SiteInst from the prototype orig from a module.
`static long`	`getCurrVal(long lutValue, int i)`
`static Path`	`getDCPAutoGenMD5FilePath(Path dcpFile, Path edfDir)` Gets the corresponding MD5 file path for a DCP that has had its EDIF file auto-generated
`static Path`	`getDefaultReadableEDIFDir(Path dcpFile)` Gets the corresponding EDIF directory created when auto generating EDIF from Vivado.
`static ArrayList<BELPin>`	`getDrivenBELPins(BELPin elementPin)` Gets the driven element pins of either a site port input or an element output pin.
`static BELPin`	`getDrivingBELPin(BELPin elementPin)` Gets the driving element pin of either a site port output or an element input pin.
`static BELPin`	`getDrivingBELPin(SitePinInst netSource)` Gets the originating driving element pin that corresponds to the given site pin.
`static Cell`	`getDrivingCell(SitePinInst netSource)` Tries to determine the driving cell within the site from the output site pin.
`static Path`	`getEDFAutoGenFilePath(Path dcpFile, Path edfDir)` Gets the path to the auto-generated EDIF file for the provided DCP and EDIF directory.
`static int`	`getInvertCol(String logicalPinName)`
`static Map<String,String>`	`getInvertiblePinMap(Series series, Unisim unisim)` Creates a map that contains pin names for keys that map to the Unisim Verilog parameter that can invert a pins value.
`static SitePinInst`	`getLegalAlternativeOutputPin(Net net)` Finds a legal/available alternative output site pin for the given net.
`static BELPin`	`getLogicalBELPinDriver(SitePinInst sitePinInst)` Looks backwards from a SitePinInst output pin and finds the corresponding BELPin of the driver.
`static Map<Node,ArrayList<PIP>>`	`getNodePIPMap(List<PIP> route)` Creates a map from Node to a list of PIPs for a given list of PIPs (likely from the routing of a net).
`static List<EDIFHierPortInst>`	`getPortInstsFromSitePinInst(SitePinInst sitePin)` Given a SitePinInst, this method will find any return hierarchical logical cell pins within the site directly connected to the site pin.
`static String`	`getRoutedSitePin(Cell cell, Net net, String logicalPinName)` Gets the first site pin that is currently routed to the specified cell pin.
`static String`	`getRoutedSitePinFromPhysicalPin(Cell cell, Net net, String belPinName)` Gets the first site pin that is currently routed to the specified cell pin.
`static String`	`getSitePinSource(BELPin pin)` Given an unroute site wire path, find the site pin name that would drive the given BELPin.
`static Set<PIP>`	`getTrimmablePIPsFromPins(Net net, Collection<SitePinInst> pins)` For the given set of pins, if they were removed, determine which PIPs could be trimmed as they no longer route to any specific sink.
`static void`	`handlePinRemovals(SitePinInst spi, Map<Net,Set<SitePinInst>> deferRemovals)` Helper method for either removing (and unrouting) a SitePinInst immediately (when deferRemovals is null) or deferring its removal by putting it into the deferRemovals map.
`static SitePinInst`	`identifyClockSource(SitePinInst netSource)` Tries to identify the clock pin source for the given user signal output by tracing back to a FF within a SLICE.
`static int`	`invertBit(int i, int col)`
`static String`	`invertLutInput(Cell lut, String physicalPinName)`
`static boolean`	`isBELALut(String elementName)`
`static boolean`	`isBELAReg(String elementName)`
`static boolean`	`isNetDrivenByHierPort(Net net)` Determine if a Net is driven by a hierarchical port, created as part of an out-of-context synthesis flow, for example.
`static boolean`	`isPinStateBEL(BELPin pin)`
`static Boolean`	`isUltraScaleSliceTop(BEL bel)` Checks the provided BEL's first letter to determine if it is in the top half of a SLICE or bottom half.
`static void`	`lockNetlist(Design design)` Locks the logical netlist of the design using the DONT_TOUCH property.
`static void`	`lockPlacement(Design design)` Locks placement of cells of a design against changes in Vivado.
`static void`	`lockPlacement(Design design, boolean lock)` Locks or unlocks all placement of a design against changes in Vivado.
`static void`	`lockRouting(Design design)` Locks all routing of a design (except GND and VCC nets) against changes in Vivado.
`static void`	`lockRouting(Design design, boolean lock)` Locks or unlocks all routing of a design (except GND and VCC nets) against changes in Vivado.
`static void`	`makeBlackBox(Design d, EDIFHierCellInst hierarchicalCell)` Turns the cell named hierarchicalCell into a blackbox and removes any associated placement and routing information associated with that instance.
`static void`	`makeBlackBox(Design d, String hierarchicalCellName)` Turns the cell named hierarchicalCellName into a blackbox and removes any associated placement and routing information associated with that instance.
`static void`	`makePhysNetNamesConsistent(Design design)` Make all of a Design's physical Net objects consistent with its logical (EDIF) netlist.
`static long`	`moveValToNewRow(long lutValue, int i, int newRow)`
`static void`	`optimizeLUT1Inverters(Design design)`
`static boolean`	`placeCell(Cell c, Design design)` Quick and dumb placement of a cell.
`static void`	`populateBlackBox(Design design, String hierarchicalCellName, Design cell)` NOTE: This method is not fully tested.
`static void`	`postBlackBoxCleanup(String hierCellName, Design design)` Attempts to rename boundary nets around the previous blackbox to follow naming convention (net is named after source).
`static void`	`prepareShellBlackBoxForRouting(Design design)` This adds PROHIBIT constraints to the design (via .XDC) that will prohibit the use of BEL sites in the same half SLICE if there are any other cells placed in it.
`static void`	`printSiteInstInfo(SiteInst siteInst, PrintStream ps)`
`static void`	`prohibitGNDSources(Design design)` Adds a PROHIBIT constraint for each LUT BEL supplying GND.
`static boolean`	`removeConnectedRouting(Net net, Node node)` Examines the routing of a net and will remove all parts of the routing that connect to the provided node.
`static void`	`replaceEncryptedCells(Design design, List<Path> netlists)` Removes all the existing encrypted cell files from a design and replaces them with the provided list and black boxes those cells.
`static String`	`resolveNetNameFromSiteWire(SiteInst inst, int siteWire)` Examines a site wire in a populated site inst for all the connected BELPins for cells occupying those BELs.
`static void`	`resolveSiteRoutingFromInContextPorts(Design design)` When importing designs that have been taken from an in-context implementation (write_checkpoint -cell), often Vivado will write out residual nets that do not necessarily exist in the module or are retaining GND/VCC routing from the parent context.
`static boolean`	`routeAlternativeOutputSitePin(Net net, SitePinInst sitePinInst)` Routes (within the site) the alternate site output pin for SLICE dual-output scenarios.
`static boolean`	`stampPlacement(Design design, Module stamp, Map<String,Site> instPlacements)` Given a design with multiple identical cell instances, place each of those instances using the stamp module template at the anchored site locations provided in instPlacements.
`static void`	`toCSV(String fileName, Design design)` Creates two CSV files based on this design, one for instances and one for nets.
`static void`	`unlockNetlist(Design design)` Unlocks the logical netlist of the design by removing the DONT_TOUCH property.
`static void`	`unlockPlacement(Design design)` Unlocks placement of cells of a design.
`static void`	`unlockRouting(Design design)` Unlocks any and all routing of a design.
`static boolean`	`unrouteAlternativeOutputSitePin(Net net)` Un-routes (within the site) the alternate source pin on the provided net.
`static List<SitePinInst>`	`unrouteCellPinSiteRouting(Cell cell, String logicalPinName)` Unroutes the site routing connected to the provided cell's logical pin.
`static void`	`unrouteDualOutputSitePinRouting(Design design)` In Series7 and UltraScale architectures, there are dual output site pin scenarios where an optional additional output can be used to drive out of the SLICE using the OUTMUX routing BEL.
`static void`	`unrouteGNDNetAndLUTSources(Design design)` Unroutes the GND net of a design and unroutes the site routing of any LUT GND sources while leaving other site routing inputs intact.
`static void`	`unroutePins(Net net, Collection<SitePinInst> pins)` Unroutes pins from a specific net by only removing the routing (PIPs) that are essential for those pins.
`static Set<PIP>`	`unrouteSourcePin(SitePinInst src)` Unroutes a SitePinInst of a net.
`static void`	`updatePinsIsRouted(Design design)` Update the SitePinInst.isRouted() value of all sink pins in the given Design.
`static void`	`updatePinsIsRouted(Net net)` Update the SitePinInst.isRouted() value of all pins on the given Net.
`static void`	`writeVerilogStub(Design design, String fileName)` Creates a verilog wrapper file for this design by examining the top level netlist.

Methods inherited from class Object
equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

- Field Detail
  - belTypeSitePinNameMapping
```
public static final Map<Series,Map<String,Pair<String,String>>> belTypeSitePinNameMapping
```
    Mapping from device Series to another mapping from FF BEL name to CKEN/SRST site pin name
- Constructor Detail
  - DesignTools
```
public DesignTools()
```
- Method Detail
  - identifyClockSource
```
public static SitePinInst identifyClockSource(SitePinInst netSource)
```
    Tries to identify the clock pin source for the given user signal output by tracing back to a FF within a SLICE. TODO - This method is not very robust.
    
    Parameters:
    
    netSource - The site pin output from which to start the clock search
    
    Returns:
    
    The source clock pin for the clock net or null if unable to determine one.
  - getClockDomain
```
public static Net getClockDomain(Design d,
                                 String edifNet)
```
  - getDrivingCell
```
public static Cell getDrivingCell(SitePinInst netSource)
```
    Tries to determine the driving cell within the site from the output site pin.
    
    Parameters:
    
    netSource - The output site pin from which to start searching
    
    Returns:
    
    The corresponding driving cell, or null if none could be found.
  - getDrivingBELPin
```
public static BELPin getDrivingBELPin(SitePinInst netSource)
```
    Gets the originating driving element pin that corresponds to the given site pin.
    
    Parameters:
    
    netSource - The source pin
    
    Returns:
    
    The corresponding element pin or null if none could be found.
  - getDrivingBELPin
```
public static BELPin getDrivingBELPin(BELPin elementPin)
```
    Gets the driving element pin of either a site port output or an element input pin.
    
    Parameters:
    
    elementPin - The element pin of interest. Cannot be a element output pin.
    
    Returns:
    
    The source element pin within the site for the given element pin.
  - getDrivenBELPins
```
public static ArrayList<BELPin> getDrivenBELPins(BELPin elementPin)
```
    Gets the driven element pins of either a site port input or an element output pin.
    
    Parameters:
    
    elementPin - The element pin of interest. Cannot be an element input pin.
    
    Returns:
    
    A list of sink element pins within the site for the given element pin.
  - getCorrespondingRBELInputPin
```
public static BELPin getCorrespondingRBELInputPin(BELPin outputPin,
                                                  SiteInst inst)
```
    Uses SitePIP information in the site instance to determine the driving input of the RBEL element output pin. There should only be one input that can affect the output and this method returns that input pin.
    
    Parameters:
    
    outputPin - The output pin on the RBEL element of interest.
    
    inst - The corresponding site instance where the pin resides.
    
    Returns:
    
    The driving input element pin on the RBEL, or null if none could be found.
  - getCorrespondingRBELOutputPin
```
public static BELPin getCorrespondingRBELOutputPin(BELPin inputPin,
                                                   SiteInst inst)
```
    Returns the element's output pin corresponding that is being driven by the provided input pin.
    
    Parameters:
    
    inputPin - The input pin of interest
    
    inst - The site instance corresponding to the element of interest
    
    Returns:
    
    The element's output pin that is driven by the provided input pin.
  - getCorrespondingBELInputPins
```
public static ArrayList<BELPin> getCorrespondingBELInputPins(BELPin outputPin,
                                                             SiteInst inst)
```
  - getCorrespondingBELOutputPins
```
public static ArrayList<BELPin> getCorrespondingBELOutputPins(BELPin inputPin,
                                                              SiteInst inst)
```
    TODO - Work in progress
    
    Parameters:
    
    inputPin -
    
    inst -
    
    Returns:
  - isBELALut
```
public static boolean isBELALut(String elementName)
```
  - isBELAReg
```
public static boolean isBELAReg(String elementName)
```
  - isPinStateBEL
```
public static boolean isPinStateBEL(BELPin pin)
```
  - invertBit
```
public static int invertBit(int i,
                            int col)
```
  - getCurrVal
```
public static long getCurrVal(long lutValue,
                              int i)
```
  - moveValToNewRow
```
public static long moveValToNewRow(long lutValue,
                                   int i,
                                   int newRow)
```
  - getInvertCol
```
public static int getInvertCol(String logicalPinName)
```
  - invertLutInput
```
public static String invertLutInput(Cell lut,
                                    String physicalPinName)
```
  - areAllPinsConnectedToALUT
```
public static boolean areAllPinsConnectedToALUT(Net n)
```
    Determines if all the pins connected to this net connect to only LUTs
    
    Returns:
    
    True if all pins connect only to LUTs, false otherwise.
  - optimizeLUT1Inverters
```
public static void optimizeLUT1Inverters(Design design)
```
  - createPinAndAddToNet
```
public static SitePinInst createPinAndAddToNet(Cell cell,
                                               String cellPinName,
                                               Net net)
```
    Creates a new pin on a site connected to the cell pin and also adds it to the provided net. Updates both logical and physical netlist representations. Note: If the site pin being added is an output it will displace any existing output source on the given net.
    
    Parameters:
    
    cell - The placed source or sink BEL instance from which to trace to a site pin. Must have a direct connection to a site pin.
    
    cellPinName - Name of the logical pin name on the cell.
    
    net - The net to add the pin to.
    
    Returns:
    
    The newly created pin that has been added to net
  - calculateUtilization
```
public static Map<UtilizationType,Integer> calculateUtilization(Design d,
                                                                PBlock pblock)
```
  - calculateUtilization
```
public static Map<UtilizationType,Integer> calculateUtilization(Design d)
```
  - calculateUtilization
```
public static Map<UtilizationType,Integer> calculateUtilization(Collection<SiteInst> siteInsts)
```
  - writeVerilogStub
```
public static void writeVerilogStub(Design design,
                                    String fileName)
```
    Creates a verilog wrapper file for this design by examining the top level netlist.
    
    Parameters:
    
    fileName - Name of the desired verilog file.
  - toCSV
```
public static void toCSV(String fileName,
                         Design design)
```
    Creates two CSV files based on this design, one for instances and one for nets.
    
    Parameters:
    
    fileName -
  - findRoutingPath
```
public static List<PIP> findRoutingPath(Node start,
                                        Node end)
```
    Demonstrates a rudimentary path expansion for finding a routing path in the interconnect.
    
    Parameters:
    
    start - Desired start node
    
    end - Desired end node
    
    Returns:
    
    A list of PIPs that configure a path from start to end nodes, or null if a path could not be found.
  - findRoutingPath
```
public static List<PIP> findRoutingPath(RouteNode start,
                                        RouteNode end)
```
    Demonstrates a rudimentary path expansion for finding a routing path in the interconnect.
    
    Parameters:
    
    start - Desired start node
    
    end - Desired end node
    
    Returns:
    
    A list of PIPs that configure a path from start to end nodes, or null if a path could not be found.
  - resolveNetNameFromSiteWire
```
public static String resolveNetNameFromSiteWire(SiteInst inst,
                                                int siteWire)
```
    Examines a site wire in a populated site inst for all the connected BELPins for cells occupying those BELs. It attempts to lookup the net attached to the cell pin in order to find the hierarchical parent net name of the net and returns its name.
    
    Parameters:
    
    inst - The site instance where the site wire in question resides.
    
    siteWire - The site wire index in the site where the site inst resides.
    
    Returns:
    
    The hierarchical parent net name using the site wire or null if none could be found.
  - populateBlackBox
```
public static void populateBlackBox(Design design,
                                    String hierarchicalCellName,
                                    Design cell)
```
    NOTE: This method is not fully tested. Populates a black box in a netlist with the provided design. This method most closely resembles the Vivado command read_checkpoint -cell <cell name> <DCP Name>
    
    Parameters:
    
    design - The top level design
    
    hierarchicalCellName - Name of the black box in the design netlist.
    
    cell - The 'guts' to be inserted into the black box
  - postBlackBoxCleanup
```
public static void postBlackBoxCleanup(String hierCellName,
                                       Design design)
```
    Attempts to rename boundary nets around the previous blackbox to follow naming convention (net is named after source).
    
    Parameters:
    
    hierCellName - The hierarchical cell instance that was previously a black box
    
    design - The current design.
  - getNodePIPMap
```
public static Map<Node,ArrayList<PIP>> getNodePIPMap(List<PIP> route)
```
    Creates a map from Node to a list of PIPs for a given list of PIPs (likely from the routing of a net).
    
    Parameters:
    
    route - The list of PIPs to create the map from.
    
    Returns:
    
    The map of all involved nodes to their respectively connected PIPs.
  - removeConnectedRouting
```
public static boolean removeConnectedRouting(Net net,
                                             Node node)
```
    Examines the routing of a net and will remove all parts of the routing that connect to the provided node. This is most useful when attempting to unroute parts of a static (VCC/GND) net that have multiple sources.
    
    Parameters:
    
    net - The net with potential disjoint routing trees
    
    node - Node belonging to the routing tree to remove.
    
    Returns:
    
    True if PIPs were removed, false otherwise
  - unroutePins
```
public static void unroutePins(Net net,
                               Collection<SitePinInst> pins)
```
    Unroutes pins from a specific net by only removing the routing (PIPs) that are essential for those pins. This allows the net to remain routed in the context of other pins not being removed. This enables a batch approach which is much more efficient than removing pins individually.
    
    Parameters:
    
    net - The current net to modify routing and to which all pins will have their routing removed. If any pin passed in is not of this net, it is skipped and no effect is taken.
    
    pins - Pins that belong to the provided net that should have their selective routing removed. Source pins are handled by DesignTools.unrouteSourcePin(SitePinInst).
  - unrouteSourcePin
```
public static Set<PIP> unrouteSourcePin(SitePinInst src)
```
    Unroutes a SitePinInst of a net. This is desirable when a net has multiple SitePinInst source pins (multiple outputs of a Site) and only a particular branch is desired to be unrouted. If the entire net is to be unrouted, a more efficient method is Net.unroute().
    
    Parameters:
    
    src - The source pin of the net from which to remove the routing
    
    Returns:
    
    The set of PIPs that were unrouted from the net.
  - getTrimmablePIPsFromPins
```
public static Set<PIP> getTrimmablePIPsFromPins(Net net,
                                                Collection<SitePinInst> pins)
```
    For the given set of pins, if they were removed, determine which PIPs could be trimmed as they no longer route to any specific sink. This method only works for sink pins. See DesignTools.unrouteSourcePin(SitePinInst) for handling source pin unroutes.
    
    Parameters:
    
    net - The current net
    
    pins - The set of pins to remove.
    
    Returns:
    
    The set of redundant (trimmable) PIPs that cane safely be removed when removing the set of provided pins from the net.
  - fullyUnplaceCell
```
public static void fullyUnplaceCell(Cell cell,
                                    Map<Net,Set<SitePinInst>> deferRemovals)
```
    This method will fully unplace (but not remove) a physical cell from a design. In the case where the unplaced cell is the last user of a shared control signal (CLK, CE, SR) then that pin will also be removed and unrouted immediately if deferRemovals is null, otherwise it is added to this map.
    
    Parameters:
    
    cell - The cell to unplace
    
    deferRemovals - An optional map that, if passed in non-null will be populated with site pins marked for removal. The map allows for persistent tracking if this method is called many times as the process is expensive without batching.
  - fullyRemoveCell
```
public static void fullyRemoveCell(Design design,
                                   Cell cell,
                                   Map<Net,Set<SitePinInst>> deferRemovals)
```
    This method will completely remove a placed cell (both logical and physical) from a design. In the case where the removed cell is the last user of a shared control signal (CLK, CE, SR) then that pin will also be removed and unrouted immediately if deferRemovals is null, otherwise it is added to this map.
    
    Parameters:
    
    design - The design where the cell is instantiated
    
    cell - The cell to remove
    
    deferRemovals - An optional map that, if passed in non-null will be populated with site pins marked for removal. The map allows for persistent tracking if this method is called many times as the process is expensive without batching.
  - handlePinRemovals
```
public static void handlePinRemovals(SitePinInst spi,
                                     Map<Net,Set<SitePinInst>> deferRemovals)
```
    Helper method for either removing (and unrouting) a SitePinInst immediately (when deferRemovals is null) or deferring its removal by putting it into the deferRemovals map.
    
    Parameters:
    
    spi - SitePinInst object to be removed/unrouted.
    
    deferRemovals - Optional map for deferring the removal of SitePinInst objects, grouped by their associated Net object.
  - getSitePinSource
```
public static String getSitePinSource(BELPin pin)
```
    Given an unroute site wire path, find the site pin name that would drive the given BELPin.
    
    Parameters:
    
    pin - The BELpin to search from
    
    Returns:
    
    Name of the site pin that would drive the given BELPin or null if it could not be determined.
  - batchRemoveSitePins
```
public static void batchRemoveSitePins(Map<Net,Set<SitePinInst>> deferredRemovals,
                                       boolean preserveOtherRoutes)
```
    Remove a batch of site pins from nets for efficiency purposes. Used in conjunction with DesignTools.fullyRemoveCell(Design, Cell, Map).
    
    Parameters:
    
    deferredRemovals - Mapping between nets and the site pins to be removed
    
    preserveOtherRoutes - Flag indicating if when pins are removed, if other routes on the net should be preserved.
  - makeBlackBox
```
public static void makeBlackBox(Design d,
                                String hierarchicalCellName)
```
    Turns the cell named hierarchicalCellName into a blackbox and removes any associated placement and routing information associated with that instance. In Vivado, this can be accomplished by running: (1) update_design -cells <name> -black_box or (2) by deleting all of the cells and nets insides of a cell instance. Method (2) is more likely to have complications.
    
    Parameters:
    
    d - The current design
    
    hierarchicalCellName - The name of the hierarchical cell to become a black box.
  - unrouteCellPinSiteRouting
```
public static List<SitePinInst> unrouteCellPinSiteRouting(Cell cell,
                                                          String logicalPinName)
```
    Unroutes the site routing connected to the provided cell's logical pin. Preserves other parts of the net if used by other sinks in the site if an input. For the unrouting to be successful, this method depends on the site routing to be consistent.
    
    Parameters:
    
    cell - The cell of the pin
    
    logicalPinName - The logical pin name source or sink to have routing removed.
  - makeBlackBox
```
public static void makeBlackBox(Design d,
                                EDIFHierCellInst hierarchicalCell)
```
    Turns the cell named hierarchicalCell into a blackbox and removes any associated placement and routing information associated with that instance. In Vivado, this can be accomplished by running: (1) update_design -cells <name> -black_box or (2) by deleting all of the cells and nets insides of a cell instance. Method (2) is more likely to have complications. This also unroutes both GND and VCC nets to avoid implementation issues by Vivado in subsequent place and route runs.
    
    Parameters:
    
    d - The current design
    
    hierarchicalCell - The hierarchical cell to become a black box.
  - getCorrespondingSiteInst
```
public static SiteInst getCorrespondingSiteInst(Design design,
                                                SiteInst orig,
                                                Site newAnchor,
                                                Module module)
```
    Gets or creates the corresponding SiteInst from the prototype orig from a module.
    
    Parameters:
    
    design - The current design from which to get the corresponding site instance.
    
    orig - The original site instance (from the module)
    
    newAnchor - The new anchor location of the module.
    
    module - The Module to use as the template.
    
    Returns:
    
    The corresponding SiteInst from design if it exists, or a newly created one in the translated location. If the new location cannot be determined or is invalid, null is returned.
  - stampPlacement
```
public static boolean stampPlacement(Design design,
                                     Module stamp,
                                     Map<String,Site> instPlacements)
```
    Given a design with multiple identical cell instances, place each of those instances using the stamp module template at the anchored site locations provided in instPlacements.
    
    Parameters:
    
    design - The top level design with identical multiple cell instances.
    
    stamp - The prototype stamp (or stencil) to use for replicated placement and routing. This must match identically with the named instances in instPlacements
    
    instPlacements - Desired locations for placements
    
    Returns:
    
    True if the procedure completed successfully, false otherwise.
  - getConnectedCells
```
public static Set<Cell> getConnectedCells(BELPin pin,
                                          SiteInst si)
```
    Looks in the site instance for cells connected to this BEL pin and SiteInst.
    
    Parameters:
    
    pin - The BELPin to examine for connected cells.
    
    si - The SiteInst to examine for connected cells.
    
    Returns:
    
    Set of connected cells to this pin.
  - getConnectedCells
```
public static Set<Cell> getConnectedCells(SitePinInst pin)
```
    Looks in the site instance for cells connected to this site pin.
    
    Parameters:
    
    pin - The SitePinInst to examine for connected cells.
    
    Returns:
    
    Set of connected cells to this pin.
  - getConnectedBELPins
```
public static Set<BELPin> getConnectedBELPins(BELPin pin,
                                              SiteInst si)
```
    Looks in the site instance for BEL pins connected to this BEL pin and SiteInst.
    
    Parameters:
    
    pin - The SitePinInst to examine for connected BEL pins.
    
    si - The SiteInst to examine for connected cells.
    
    Returns:
    
    Set of BEL pins to this site pin.
  - getConnectedBELPins
```
public static Set<BELPin> getConnectedBELPins(SitePinInst pin)
```
    Looks in the site instance for BEL pins connected to this site pin.
    
    Parameters:
    
    pin - The SitePinInst to examine for connected BEL pins.
    
    Returns:
    
    Set of BEL pins to this site pin.
  - placeCell
```
public static boolean placeCell(Cell c,
                                Design design)
```
    Quick and dumb placement of a cell. Does not attempt any optimization and will not change the placement of other cells. Currently it will only place a cell in an empty site. If the cell is already placed, it will leave it as is. TODO - implement basic optimizations
    
    Parameters:
    
    c - The cell to place
    
    Returns:
    
    True if the cell is successfully placed, false otherwise.
  - createMissingSitePinInsts
```
public static List<SitePinInst> createMissingSitePinInsts(Design design,
                                                          Net net)
```
    Creates any and all missing SitePinInsts for this net. This is common as a placed DCP will not have SitePinInsts annotated and this information is generally necessary for routing to take place.
    
    Parameters:
    
    design - The current design of this net.
    
    Returns:
    
    The list of pins that were created or an empty list if none were created.
  - getRoutedSitePin
```
public static String getRoutedSitePin(Cell cell,
                                      Net net,
                                      String logicalPinName)
```
    Gets the first site pin that is currently routed to the specified cell pin. If the site instance is not routed, it will return null.
    
    Parameters:
    
    cell - The cell with the pin of interest.
    
    net - The physical net to which this pin belongs
    
    logicalPinName - The logical pin name of the cell to query.
    
    Returns:
    
    The name of the first site pin on the cell's site to which the pin is routed.
  - getRoutedSitePinFromPhysicalPin
```
public static String getRoutedSitePinFromPhysicalPin(Cell cell,
                                                     Net net,
                                                     String belPinName)
```
    Gets the first site pin that is currently routed to the specified cell pin. If the site instance is not routed, it will return null.
    
    Parameters:
    
    cell - The cell with the pin of interest.
    
    net - The physical net to which this pin belongs
    
    belPinName - The physical pin name of the cell
    
    Returns:
    
    The name of the first site pin on the cell's site to which the pin is routed.
  - getAllRoutedSitePinsFromPhysicalPin
```
public static List<String> getAllRoutedSitePinsFromPhysicalPin(Cell cell,
                                                               Net net,
                                                               String belPinName)
```
    Gets all site pins that are currently routed to the specified cell pin. If the site instance is not routed, it will return null.
    
    Parameters:
    
    cell - The cell with the pin of interest.
    
    net - The physical net to which this pin belongs
    
    belPinName - The physical pin name of the cell
    
    Returns:
    
    A list of site pin names on the cell's site to which the pin is routed.
    
    Since:
    
    2023.1.2
  - createMissingSitePinInsts
```
public static void createMissingSitePinInsts(Design design)
```
    Creates all missing SitePinInsts in a design, except GLOBAL_USEDNET. See also DesignTools.createMissingSitePinInsts(Design, Net).
    
    Parameters:
    
    design - The current design
  - unrouteDualOutputSitePinRouting
```
public static void unrouteDualOutputSitePinRouting(Design design)
```
    In Series7 and UltraScale architectures, there are dual output site pin scenarios where an optional additional output can be used to drive out of the SLICE using the OUTMUX routing BEL. When unrouting a design, some site routing can be left "dangling". This method will remove those unnecessary sitePIPs and site routing for the *MUX output. It will also remove the output source pin if it is the *MUX output.
    
    Parameters:
    
    design - The design from which to remove the unnecessary site routing
  - getLegalAlternativeOutputPin
```
public static SitePinInst getLegalAlternativeOutputPin(Net net)
```
    Finds a legal/available alternative output site pin for the given net. The most common case is the SLICE. It depends on the existing output pin of the net to be routed within the site and checks if site routing resource are available to use the alternative output site pin.
    
    Parameters:
    
    net - The net of interest.
    
    Returns:
    
    A new potential site pin inst that could be added/routed to.
  - getLogicalBELPinDriver
```
public static BELPin getLogicalBELPinDriver(SitePinInst sitePinInst)
```
    Looks backwards from a SitePinInst output pin and finds the corresponding BELPin of the driver.
    
    Parameters:
    
    sitePinInst - The output site pin instance from which to find the logical driver.
    
    Returns:
    
    The logical driver's BELPin of the provided sitePinInst.
  - routeAlternativeOutputSitePin
```
public static boolean routeAlternativeOutputSitePin(Net net,
                                                    SitePinInst sitePinInst)
```
    Routes (within the site) the alternate site output pin for SLICE dual-output scenarios.
    
    Parameters:
    
    net - The current net of interest to be routed
    
    sitePinInst - The alternate site output pin to be routed
    
    Returns:
    
    True if the routing was successful, false otherwise
  - unrouteAlternativeOutputSitePin
```
public static boolean unrouteAlternativeOutputSitePin(Net net)
```
    Un-routes (within the site) the alternate source pin on the provided net. This is in reference to dual-output site pin scenarios for SLICEs.
    
    Parameters:
    
    net - The relevant net that has the populated alternative site pin.
    
    Returns:
    
    True if the alternate source was unrouted successfully, false otherwise.
  - getPortInstsFromSitePinInst
```
public static List<EDIFHierPortInst> getPortInstsFromSitePinInst(SitePinInst sitePin)
```
    Given a SitePinInst, this method will find any return hierarchical logical cell pins within the site directly connected to the site pin.
    
    Parameters:
    
    sitePin - The site pin to query.
    
    Returns:
    
    A list of hierarchical port instances that connect to the site pin.
  - getInvertiblePinMap
```
public static Map<String,String> getInvertiblePinMap(Series series,
                                                     Unisim unisim)
```
    Creates a map that contains pin names for keys that map to the Unisim Verilog parameter that can invert a pins value.
    
    Parameters:
    
    series - The series of interest.
    
    unisim - The unisim of interest.
    
    Returns:
    
    A map of invertible pins that are that are mapped to their respective parameter name that controls inversion.
  - copyImplementation
```
public static void copyImplementation(Design src,
                                      Design dest,
                                      boolean lockPlacement,
                                      boolean lockRouting,
                                      Map<String,String> srcToDestInstNames)
```
    Copies the logic and implementation of a set of cells from one design to another. This will replace the destination logical cell instances with those of the source design.
    
    Parameters:
    
    src - The source design (with partial or full implementation)
    
    dest - The destination design (with matching cell instance interfaces).
    
    lockPlacement - Flag indicating if the destination implementation copy should have the placement locked
    
    lockRouting - Flag indicating if the destination implementation copy should have the routing locked
    
    srcToDestInstNames - A map of source (key) to destination (value) pairs of cell instances from which to copy the implementation. If targeting the top instance, use an empty String ("") as the destination instance name.
  - copyImplementation
```
public static void copyImplementation(Design src,
                                      Design dest,
                                      boolean copyStaticNets,
                                      boolean copyOnlyInternalNets,
                                      boolean lockPlacement,
                                      boolean lockRouting,
                                      Map<String,String> srcToDestInstNames)
```
    Copies the logic and implementation of a set of cells from one design to another with additional flags to control copying nets.
    
    Parameters:
    
    src - The source design (with partial or full implementation)
    
    dest - The destination design (with matching cell instance interfaces)
    
    copyStaticNets - Flag indicating if static nets should be copied
    
    copyOnlyInternalNets - Flag indicating if only nets with every terminal inside the cell should be copied
    
    lockPlacement - Flag indicating if the destination implementation copy should have the placement locked
    
    lockRouting - Flag indicating if the destination implementation copy should have the routing locked
    
    srcToDestInstNames - A map of source (key) to destination (value) pairs of cell instances from which to copy the implementation
  - copyImplementation
```
public static void copyImplementation(Design src,
                                      Design dest,
                                      String... instNames)
```
    Copies the logic and implementation of a set of cells from one design to another.
    
    Parameters:
    
    src - The source design (with partial or full implementation)
    
    dest - The destination design (with matching cell instance interfaces)
    
    instNames - Names of the cell instances to copy
  - copyImplementation
```
public static void copyImplementation(Design src,
                                      Design dest,
                                      boolean lockPlacement,
                                      boolean lockRouting,
                                      String... instNames)
```
    Copies the logic and implementation of a set of cells from one design to another.
    
    Parameters:
    
    src - The source design (with partial or full implementation)
    
    dest - The destination design (with matching cell instance interfaces)
    
    lockPlacement - Flag indicating if the destination implementation copy should have the placement locked
    
    lockRouting - Flag indicating if the destination implementation copy should have the routing locked
    
    instNames - Names of the cell instances to copy
  - printSiteInstInfo
```
public static void printSiteInstInfo(SiteInst siteInst,
                                     PrintStream ps)
```
  - makePhysNetNamesConsistent
```
public static void makePhysNetNamesConsistent(Design design)
```
    Make all of a Design's physical Net objects consistent with its logical (EDIF) netlist. Specifically, merge all sitewire and SitePinInst-s associated with physical Net-s that are not the parent/canonical logical net into the parent Net, and delete all non-parent Net-s.
    
    Parameters:
    
    design - Design object to be modified in-place.
  - createPossiblePinsToStaticNets
```
public static void createPossiblePinsToStaticNets(Design design)
```
  - createCeClkOfRoutethruFFToVCC
```
public static void createCeClkOfRoutethruFFToVCC(Design design)
```
  - createA1A6ToStaticNets
```
public static void createA1A6ToStaticNets(Design design)
```
  - createCeSrRstPinsToVCC
```
public static void createCeSrRstPinsToVCC(Design design)
```
    Create and add any missing SitePinInst-s belonging to the VCC net. This is indicated by the sitewire corresponding to CE and SR pins of SLICE FFs, or to the RST pins on RAMBs, having no associated net.
    
    Parameters:
    
    design - Design object to be modified in-place.
  - createMissingStaticSitePins
```
public static void createMissingStaticSitePins(BELPin belPin,
                                               SiteInst si,
                                               Cell cell)
```
  - getConnectionPIPs
```
public static List<PIP> getConnectionPIPs(SitePinInst sinkPin)
```
    Finds the essential PIPs which connect the provided sink pin to its source.
    
    Parameters:
    
    sinkPin - A sink pin from a routed net.
    
    Returns:
    
    The list of PIPs that for the routing connection from the sink to the source.
  - generateReadableEDIFJob
```
public static Job generateReadableEDIFJob(Path checkpoint,
                                          Path edif)
```
    Create a Job running Vivado to create a readable version of the EDIF inside the checkpoint to a separate file.
    
    Parameters:
    
    checkpoint - the input checkpoint
    
    edif - the output EDIF
    
    Returns:
    
    the created Job
  - getDefaultReadableEDIFDir
```
public static Path getDefaultReadableEDIFDir(Path dcpFile)
```
    Gets the corresponding EDIF directory created when auto generating EDIF from Vivado.
    
    Parameters:
    
    dcpFile - The source DCP file path
    
    Returns:
    
    The directory where auto generated .edf and .edn files go.
  - getDCPAutoGenMD5FilePath
```
public static Path getDCPAutoGenMD5FilePath(Path dcpFile,
                                            Path edfDir)
```
    Gets the corresponding MD5 file path for a DCP that has had its EDIF file auto-generated
    
    Parameters:
    
    dcpFile - The Path to the DCP source
    
    edfDir - The directory containing the auto-generated edf and md5 file
    
    Returns:
    
    The path to the MD5 file
  - getEDFAutoGenFilePath
```
public static Path getEDFAutoGenFilePath(Path dcpFile,
                                         Path edfDir)
```
    Gets the path to the auto-generated EDIF file for the provided DCP and EDIF directory.
    
    Parameters:
    
    dcpFile - The Path to the DCP source
    
    edfDir - The directory where the auto-generated EDIF is stored
    
    Returns:
    
    The path to the auto-generated EDIF file
  - generateReadableEDIF
```
public static Path generateReadableEDIF(Path dcp,
                                        Path edfFileName)
```
    Use Vivado to create a readable version of the EDIF file inside a design checkpoint. If no edf file name is provided (edfFileName=null), it will manage over-written DCPs with an md5 hash so that edf can stay in sync with a DCP.
    
    Parameters:
    
    dcp - the checkpoint
    
    edfFileName - filename to use or null if we should select a filename
    
    Returns:
    
    the readable output edif filename
  - resolveSiteRoutingFromInContextPorts
```
public static void resolveSiteRoutingFromInContextPorts(Design design)
```
    When importing designs that have been taken from an in-context implementation (write_checkpoint -cell), often Vivado will write out residual nets that do not necessarily exist in the module or are retaining GND/VCC routing from the parent context. This method will resolve conflicts by examining the site routing leading from input ports to the sinks and update the site routing to the appropriate net as dictated in the new design. GND and VCC will be replaced by the name of the source net being driven by the input ports.
    
    Parameters:
    
    design - The design of interest.
  - createModuleImplsInst
```
public static ModuleImplsInst createModuleImplsInst(Design design,
                                                    String name,
                                                    ModuleImpls module)
```
    Create a ModuleImplsInst, i.e. a Module instance with flexible implementation. If an edif cell inst of the given name already exists in the design hierarchy, it will be used for the module. Otherwise, a new EDIF Cell Inst will be created.
    
    Parameters:
    
    design - the design
    
    name - name of the module instance
    
    module - the module to use
    
    Returns:
    
    the newly created instance
  - createModuleInstsFromModuleImplsInsts
```
public static void createModuleInstsFromModuleImplsInsts(Design design,
                                                         Collection<ModuleImplsInst> instances,
                                                         Collection<ImplsPath> paths)
```
    In a design containing ModuleImplsInsts, convert them into ModuleInsts so that the design can be exported to a checkpoint
    
    Parameters:
    
    design - the design
    
    instances - the instances to be converted
    
    paths - nets connecting the instances as returned by BlockPlacer2.getPaths()
  - isNetDrivenByHierPort
```
public static boolean isNetDrivenByHierPort(Net net)
```
    Determine if a Net is driven by a hierarchical port, created as part of an out-of-context synthesis flow, for example.
    
    Parameters:
    
    net - Net to examine.
    
    Returns:
    
    True if driven by a hierport.
  - lockNetlist
```
public static void lockNetlist(Design design)
```
    Locks the logical netlist of the design using the DONT_TOUCH property. This strives to be as close as possible to what Vivado's 'lock_design -level netlist' does to lock the design. EDIFTools.lockNetlist(EDIFNetlist).
    
    Parameters:
    
    design - The design of the netlist to lock.
  - unlockNetlist
```
public static void unlockNetlist(Design design)
```
    Unlocks the logical netlist of the design by removing the DONT_TOUCH property. This strives to be as close as possible to what Vivado's 'lock_design -unlock -level netlist' does to lock the design.EDIFTools.unlockNetlist(EDIFNetlist).
    
    Parameters:
    
    design - The design of the netlist to unlock.
  - lockPlacement
```
public static void lockPlacement(Design design,
                                 boolean lock)
```
    Locks or unlocks all placement of a design against changes in Vivado. It will also lock or unlock the netlist of the design (see DesignTools.lockNetlist(Design)). This strives to be as close as possible to what Vivado's 'lock_design -level placement' does to lock the design.
    
    Parameters:
    
    design - The design to lock
    
    lock - Flag indicating to lock (true) or unlock (false) the design's placement and netlist.
  - lockPlacement
```
public static void lockPlacement(Design design)
```
    Locks placement of cells of a design against changes in Vivado. It will also lock the netlist the design (see DesignTools.lockNetlist(Design)). This strives to be as close as possible to what Vivado's 'lock_design -level placement' does to lock the design.
    
    Parameters:
    
    design - The design to lock
  - unlockPlacement
```
public static void unlockPlacement(Design design)
```
    Unlocks placement of cells of a design. It will also unlock the netlist the design (see DesignTools.unlockNetlist(Design)). This strives to be as close as possible to what Vivado's 'lock_design -unlock -level placement' does to lock the design.
    
    Parameters:
    
    design - The design to unlock
  - lockRouting
```
public static void lockRouting(Design design,
                               boolean lock)
```
    Locks or unlocks all routing of a design (except GND and VCC nets) against changes in Vivado. It will also lock or unlock the netlist and placement of the design (see DesignTools.lockPlacement(Design, boolean)). This strives to be as close as possible to what Vivado's 'lock_design -level routing' does to lock the design.
    
    Parameters:
    
    design - The design to lock
    
    lock - Flag indicating to lock (true) or unlock (false) the design's routing, placement and netlist.
  - lockRouting
```
public static void lockRouting(Design design)
```
    Locks all routing of a design (except GND and VCC nets) against changes in Vivado. It will also lock the netlist and placement of the design. This strives to be as close as possible to what Vivado's 'lock_design -level routing' does to lock the design.
    
    Parameters:
    
    design - The design to lock
  - unlockRouting
```
public static void unlockRouting(Design design)
```
    Unlocks any and all routing of a design. It will also unlock the netlist and placement of the design. This strives to be as close as possible to what Vivado's 'lock_design -unlock -level routing' does to lock the design.
    
    Parameters:
    
    design - The design to unlock
  - unrouteGNDNetAndLUTSources
```
public static void unrouteGNDNetAndLUTSources(Design design)
```
    Unroutes the GND net of a design and unroutes the site routing of any LUT GND sources while leaving other site routing inputs intact.
    
    Parameters:
    
    design - The design to modify.
  - prohibitGNDSources
```
public static void prohibitGNDSources(Design design)
```
    Adds a PROHIBIT constraint for each LUT BEL supplying GND. This is useful when trying to preserve a partially implemented design that have additional logic placed and routed onto it later. The Vivado placer doesn't recognize the GND sources so this prevents the placer from using those BEL sites.
    
    Parameters:
    
    design - The design to which the PROHIBIT constraints are added.
  - isUltraScaleSliceTop
```
public static Boolean isUltraScaleSliceTop(BEL bel)
```
    Checks the provided BEL's first letter to determine if it is in the top half of a SLICE or bottom half.
    
    Parameters:
    
    bel - The BEL of a SLICE to query
    
    Returns:
    
    True if the BEL resides in the top half of a SLICE (E6LUT, E5LUT, EFF, EFF2, ..). Returns false if it is in the bottom half and null if it couldn't be determined.
  - prepareShellBlackBoxForRouting
```
public static void prepareShellBlackBoxForRouting(Design design)
```
    This adds PROHIBIT constraints to the design (via .XDC) that will prohibit the use of BEL sites in the same half SLICE if there are any other cells placed in it. It also detects unroutable situations on flip flop inputs and inserts LUT1-routethrus into the netlist. It will also add PROHIBIT constraints onto flip flop sites that are unroutable. This is used for shell creation when an existing placed and routed implementation is desired to be preserved but to allow additional logic to be placed and routed on top of it without an area (pblock) constraint.
    
    Parameters:
    
    design - The design to which the constraints are added.
  - addProhibitConstraint
```
public static void addProhibitConstraint(Design design,
                                         List<String> belLocations)
```
    Adds a PROHIBIT constraint to the specified BEL Locations (ex: "SLICE_X10Y10/AFF")
    
    Parameters:
    
    design - The design to which the constraint should be added
    
    belLocations - A list of BEL locations using the syntax '<SITE-NAME>/<BEL-NAME>'.
  - updatePinsIsRouted
```
public static void updatePinsIsRouted(Net net)
```
    Update the SitePinInst.isRouted() value of all pins on the given Net. A sink pin will be marked as being routed if it is reachable from the Net's source pins (or in the case of static nets, also from nodes tied to GND or VCC) when following the Net's PIPs. A source pin will be marked as being routed if it drives at least one PIP.
    
    Parameters:
    
    net - Net on which pins are to be updated.
  - updatePinsIsRouted
```
public static void updatePinsIsRouted(Design design)
```
    Update the SitePinInst.isRouted() value of all sink pins in the given Design. See DesignTools.updatePinsIsRouted(Net).
    
    Parameters:
    
    design - Design in which pins are to be updated.
  - replaceEncryptedCells
```
public static void replaceEncryptedCells(Design design,
                                         List<Path> netlists)
```
    Removes all the existing encrypted cell files from a design and replaces them with the provided list and black boxes those cells. The provided files should be named after the cell type. This is useful in the scenarios where a design has many thousand of individual encrypted cell files that are time consuming to load. By providing a higher level of hierarchy cell definition, encompassing all existing encrypted cells, the number of individual files to be loaded by Vivado can be reduced.
    
    Parameters:
    
    design - The design to modify.
    
    netlists - The list of encrypted cell files (*.edn, *.edf, or *.dcp) that should be used instead.

Class DesignTools

Field Summary

Constructor Summary

Method Summary

Methods inherited from class Object

Field Detail

belTypeSitePinNameMapping

Constructor Detail

DesignTools

Method Detail

identifyClockSource

getClockDomain

getDrivingCell

getDrivingBELPin

getDrivingBELPin

getDrivenBELPins

getCorrespondingRBELInputPin

getCorrespondingRBELOutputPin

getCorrespondingBELInputPins

getCorrespondingBELOutputPins

isBELALut

isBELAReg

isPinStateBEL

invertBit

getCurrVal

moveValToNewRow

getInvertCol

invertLutInput

areAllPinsConnectedToALUT

optimizeLUT1Inverters

createPinAndAddToNet

calculateUtilization

calculateUtilization

calculateUtilization

writeVerilogStub

toCSV

findRoutingPath

findRoutingPath

resolveNetNameFromSiteWire

populateBlackBox

postBlackBoxCleanup

getNodePIPMap

removeConnectedRouting

unroutePins

unrouteSourcePin

getTrimmablePIPsFromPins

fullyUnplaceCell

fullyRemoveCell

handlePinRemovals

getSitePinSource

batchRemoveSitePins

makeBlackBox

unrouteCellPinSiteRouting

makeBlackBox

getCorrespondingSiteInst

stampPlacement

getConnectedCells

getConnectedCells

getConnectedBELPins

getConnectedBELPins

placeCell

createMissingSitePinInsts

getRoutedSitePin

getRoutedSitePinFromPhysicalPin

getAllRoutedSitePinsFromPhysicalPin

createMissingSitePinInsts

unrouteDualOutputSitePinRouting

getLegalAlternativeOutputPin

getLogicalBELPinDriver

routeAlternativeOutputSitePin

unrouteAlternativeOutputSitePin

getPortInstsFromSitePinInst

getInvertiblePinMap

copyImplementation

copyImplementation

copyImplementation

copyImplementation

printSiteInstInfo

makePhysNetNamesConsistent

createPossiblePinsToStaticNets