public class Net extends Object implements Comparable<Net>, Serializable
DesignTools.makePhysNetNamesConsistent(com.xilinx.rapidwright.design.Design)
to fix these issues.Modifier and Type | Field and Description |
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static String |
GND_NET
Name of the global physical GND net
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static String |
GND_WIRE_NAME
Name of the common GND source wire name
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static String |
USED_NET
Name of the global physical USED net
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static String |
VCC_NET
Name of the global physical VCC net
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static String |
VCC_WIRE_NAME
Name of the common VCC source wire name
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static String |
Z_NET
Name of the global dummy route (Z) net
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Constructor and Description |
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Net()
Default Constructor
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Net(EDIFHierNet net)
Creates a new physical net based on an existing logical net.
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Net(String name)
Initializing constructor, does not create a logical net, nor populates
it.
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Net(String name,
EDIFHierNet logicalHierNet)
Creates a new physical net based on an existing logical net.
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Net(String name,
NetType type)
Creates a new physical net with the ability to specify its type.
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Modifier and Type | Method and Description |
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boolean |
addPin(SitePinInst sitePinInst)
Adds a new pin to the net.
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boolean |
addPin(SitePinInst sitePinInst,
boolean updateSiteRouting)
Adds a new pin to the net.
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boolean |
addPins(List<SitePinInst> pinsToAdd)
Adds a list of pins to the net.
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void |
addPIP(PIP pip)
Adds a PIP to the net.
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int |
compareTo(Net o)
Compares two nets based on fan-out.
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SitePinInst |
connect(Cell c,
String logicalPinName)
Makes both logical and physical connections (EDIFNet and Net) for
a logical pin on the given cell.
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SitePinInst |
createPin(String pinName,
SiteInst si)
Convenience function that creates a new pin from the provided parameters
and adds it to the net.
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void |
detachFromModule()
This method will detach and remove all reference of the net to a module
or module instance.
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boolean |
equals(Object obj)
Checks if two nets are equal by name.
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SitePinInst |
getAlternateSource()
Gets the alternate site pin (if set) on this net.
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int |
getBufferDelay(Site site)
Gets the specified clock buffer delay.
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List<PIP> |
getCopyOfPIPs()
Gets a complete copy of the PIPs of this net.
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Design |
getDesign()
Gets the design to which this net belongs.
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int |
getFanOut()
Gets the fan-out (number of sinks) of the net.
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EDIFHierNet |
getLogicalHierNet()
Gets the logical hierarchical net that corresponds to this physical net.
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EDIFNet |
getLogicalNet()
Gets the logical EDIF netlist equivalent net.
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ModuleInst |
getModuleInst()
Gets and returns the nets current module instance it belongs to.
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Module |
getModuleTemplate()
Gets the module template this net is a member of
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Net |
getModuleTemplateNet()
Gets and returns the net found in the module which this net implements.
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String |
getName()
Gets and return the current net name (the physical hierarchical name of the net).
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List<SitePinInst> |
getPins()
Gets the site pins (source and sinks) of the net.
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List<PIP> |
getPIPs()
Gets the PIPs (routing resources) used by the net.
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List<SitePinInst> |
getSinkPins()
Gets all the sink pins on the net (no sources).
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Set<SiteInst> |
getSiteInsts()
Gets the set of SiteInsts that connect to or are routed by this net.
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SitePinInst |
getSource()
Gets and returns the source of the net.
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Tile |
getSourceTile()
Gets and returns the tile where the source pin resides.
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NetType |
getType()
Gets and returns the type of the net.
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boolean |
hasGapRouting()
Checks if this net has gap routing, most commonly used to represent clock planning intentions
that are stored after placement but before routing a design in Vivado.
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int |
hashCode()
Creates a hashCode for the net based on its name.
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boolean |
hasPIPs()
Checks if the net has any PIPs.
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void |
improveSLRClockingDelay(String txClkWire,
String rxClkWire)
Optimizes clocking buffers to manage hold delay violations when using both
TX and RX Laguna flops.
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boolean |
isClockNet()
Checks if the net is a clock net.
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boolean |
isGNDNet()
Checks if this net is the main GND net (GLOBAL_LOGIC0).
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boolean |
isStaticNet()
Checks if the net is a static net (source is VCC/GND).
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boolean |
isUsedNet()
Checks if this net is the main Used net (GLOBAL_USEDNET).
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boolean |
isVCCNet()
Checks if this net is the main VCC net (GLOBAL_LOGIC1).
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void |
lockRouting()
Locks or fixes the routing such that Vivado cannot change the route
until the flag is removed.
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boolean |
needsClockNetworkResources()
Checks if a net is a clk net and should use the clock routing resources.
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boolean |
removePin(SitePinInst sitePinInst)
Removes a pin from the list of pins in the net.
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boolean |
removePin(SitePinInst sitePinInst,
boolean preserveOtherRoutes)
Removes a pin from the list of pins in the net.
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boolean |
removePIP(PIP pip)
Removes a PIP from the net.
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void |
removeSource()
Removes the source of the net.
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boolean |
rename(String newName)
Updates the physical net to the name provided.
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SitePinInst |
replaceSource(SitePinInst newSource)
Replaces the current source with the new source and
adds it to the pin list in the net.
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void |
setAlternateSource(SitePinInst altSource)
Allow the net to be set with an alternate source pin for dual output scenarios.
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boolean |
setBufferDelay(Site site,
int value)
Sets the clock buffer delay at the referenced site to the value provided for the associated
net/routing.
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void |
setDesign(Design design)
Sets the design to which this net belongs.
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void |
setHasGapRouting(boolean hasGapRouting)
Sets the flag indicating that this route is using gap nodes.
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void |
setLogicalHierNet(EDIFHierNet logicalHierNet)
Explicitly sets the logical hierarchical net corresponding to this physical net
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void |
setModuleInst(ModuleInst moduleInst)
Sets the module instance which this net belongs to.
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void |
setModuleTemplate(Module module)
Sets the module class this net implements.
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void |
setModuleTemplateNet(Net moduleTemplateNet)
Sets the reference to the template net from a module template corresponding to this net.
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void |
setName(String name)
Sets the name of the net.
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boolean |
setPins(List<SitePinInst> list)
Sets the pins (source and sinks) of the net.
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void |
setPIPs(List<PIP> list)
Sets the PIPs of the net.
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void |
setPIPs(Set<PIP> setOfPIPs)
Sets the PIPs of the net.
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void |
setSource(SitePinInst source)
Sets the source of this net with the provided pin
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void |
setType(NetType type)
Sets the type of the net.
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String |
toString() |
String |
toStringFull()
Creates a string representation of the net (for debugging).
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void |
trimPartitionPins(Pair<Tile,Tile> range)
Remove partition pin routing beyond the first node in range.
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void |
unlockRouting()
Unlocks or unfixes the routing such that Vivado can change the route.
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void |
unroute()
This removes all PIPs from this net, causing it to be in an unrouted state.
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void |
unroutePin(SitePinInst p)
Unroute from given pin to the nearest branch of its net.
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boolean |
updateName(String newName)
Updates the net name, such as when instantiating this net in a larger
design to add a prefix.
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public static final String VCC_NET
public static final String GND_NET
public static final String USED_NET
public static final String Z_NET
public static final String VCC_WIRE_NAME
public static final String GND_WIRE_NAME
public Net()
public Net(String name)
Design#createNet()
instead.name
- Name of the new netpublic Net(String name, EDIFHierNet logicalHierNet)
name
- Name of the physical netlogicalHierNet
- The full hierarchical netpublic Net(String name, NetType type)
name
- Name of the new nettype
- Type of the new netpublic Net(EDIFHierNet net)
net
- The full hierarchical netpublic String getName()
Vivado Tcl:
get_property NAME $this
public NetType getType()
Vivado Tcl:
get_property TYPE $this
public List<SitePinInst> getPins()
Vivado Tcl:
get_site_pins -of $this
public List<PIP> getPIPs()
Vivado Tcl:
get_pips -of $this
public int getFanOut()
Vivado Tcl:
expr [llength [get_site_pins -of $this]] - 1
public boolean hasPIPs()
Vivado Tcl:
llength [get_pips -of $this] > 0
public void setName(String name)
name
- New name of the net.public boolean updateName(String newName)
public Design getDesign()
public void setDesign(Design design)
public void setType(NetType type)
type
- New type of the net.public boolean setPins(List<SitePinInst> list)
list
- The new pin list.public void setPIPs(Set<PIP> setOfPIPs)
Vivado Tcl:
set_property FIXED_ROUTE $setOfPIPs $this
setOfPIPs
- The set of PIPs for the routingpublic List<PIP> getCopyOfPIPs()
public void setPIPs(List<PIP> list)
Vivado Tcl:
set_property FIXED_ROUTE $setOfPIPs $this
setOfPIPs
- The new list of PIPs.public SitePinInst createPin(String pinName, SiteInst si)
Vivado Tcl:
set p [create_pin -direction $isOutput $pinName]; connect_net -net $this $p
pinName
- Name of the pin to createsi
- The site instance to which the newly created pin belongspublic SitePinInst connect(Cell c, String logicalPinName)
Vivado Tcl:
connect_net -net $this [get_pins $c/$logicalPinName]
c
- The cell of interest to connect to this net.logicalPinName
- Name of the logical pin on the cell.public boolean addPin(SitePinInst sitePinInst)
Vivado Tcl:
connect_net -net $this $pin
sitePinInst
- The new pin to add.public SitePinInst getAlternateSource()
public void setAlternateSource(SitePinInst altSource)
altSource
- The other source to be set.public boolean addPin(SitePinInst sitePinInst, boolean updateSiteRouting)
Vivado Tcl:
connect_net -net $this $pin
sitePinInst
- The new pin to add.updateSiteRouting
- Will route the appropriate site wirespublic boolean addPins(List<SitePinInst> pinsToAdd)
Vivado Tcl:
connect_net -net $this $pinsToAdd
pinsToAdd
- The list of new pins to add.public boolean removePin(SitePinInst sitePinInst)
Vivado Tcl:
remove_pin $pin
sitePinInst
- The pin to remove.public boolean removePin(SitePinInst sitePinInst, boolean preserveOtherRoutes)
Vivado Tcl:
remove_pin $pin
sitePinInst
- The pin to remove.preserveOtherRoutes
- Set true to only unroute part of net that supplies
removed pin.public void unroutePin(SitePinInst p)
Vivado Tcl:
route_design -unroute -pins $this
p
- The pin to unroute.public void trimPartitionPins(Pair<Tile,Tile> range)
range
- Pair of tiles on opposing corners of partpin range.public void addPIP(PIP pip)
Vivado Tcl:
set r [get_property FIXED_ROUTE $this]; set p [get_pips_from $r]; set_property FIXED_ROUTE [lappend $r $p] $this
pip
- The PIP to add.public boolean removePIP(PIP pip)
Vivado Tcl:
set r [get_property FIXED_ROUTE $this]; set p [get_pips_from $r]; set i [lsearch $r $pip]; set r [lreplace $r $i $i]; set_property FIXED_ROUTE $r $this
pip
- The PIP to remove.public boolean isStaticNet()
Vivado Tcl:
set t [get_property TYPE $this]; expr {$t eq "GROUND" || $t eq "POWER"}
public boolean isVCCNet()
public boolean isGNDNet()
public boolean isUsedNet()
public boolean needsClockNetworkResources()
Vivado Tcl:
set t [get_property TYPE $this]; string matches $t "CLOCK"
public void removeSource()
public void setSource(SitePinInst source)
source
- Desired source pinpublic SitePinInst replaceSource(SitePinInst newSource)
newSource
- The new source of the net.public SitePinInst getSource()
public Tile getSourceTile()
public void unroute()
Vivado Tcl:
route_design -unroute -nets $this
public Module getModuleTemplate()
public void setModuleTemplate(Module module)
module
- The module which this net implements.public void setModuleTemplateNet(Net moduleTemplateNet)
moduleTemplateNet
- The template net in the module to which this
net corresponds.public Net getModuleTemplateNet()
public void setModuleInst(ModuleInst moduleInst)
moduleInst
- The nets new moduleInst.public ModuleInst getModuleInst()
public void detachFromModule()
public void lockRouting()
Vivado Tcl:
set_property IS_ROUTING_FIXED 1 $this
public void unlockRouting()
Vivado Tcl:
set_property IS_ROUTING_FIXED 0 $this
public EDIFNet getLogicalNet()
public void setLogicalHierNet(EDIFHierNet logicalHierNet)
logicalHierNet
- The logical hierarchical net to setpublic EDIFHierNet getLogicalHierNet()
public int compareTo(Net o)
compareTo
in interface Comparable<Net>
public String toString()
toString
in class Object
public String toStringFull()
public int hashCode()
hashCode
in class Object
public boolean equals(Object obj)
equals
in class Object
public Set<SiteInst> getSiteInsts()
public boolean isClockNet()
Vivado Tcl:
set t [get_property TYPE $this]; string matches $t "CLOCK"
public List<SitePinInst> getSinkPins()
Vivado Tcl:
get_site_pins -of $this -filter DIRECTION==IN]
public boolean setBufferDelay(Site site, int value)
Vivado Tcl:
set s [get_property FIXED_ROUTE $this]; replace_lcb_delay_in_route_string $s; set_property FIXED_ROUTE $s $this
site
- The leaf clock buffer sitevalue
- The delay value to set on the clock buffers (for UltraScale+, valid values are: 0,1,2,4,8).public int getBufferDelay(Site site)
Vivado Tcl:
set s [get_property FIXED_ROUTE $this]; get_lcb_delay_in_route_string $site $s
site
- The clock buffer sitepublic void improveSLRClockingDelay(String txClkWire, String rxClkWire)
Vivado Tcl:
route_design #final phase
txClkWire
- TX Clock resource track (ex: GCLK_B_0_0)rxClkWire
- RX Clock resource track (ex: GCLK_B_0_1)public boolean rename(String newName)
newName
- New desired physical name of the net.public boolean hasGapRouting()
public void setHasGapRouting(boolean hasGapRouting)
hasGapRouting
- The desired flag which should represent the current state of routing
using GAP nodes.