Serialized Form

Package com.xilinx.rapidwright.design
- Class com.xilinx.rapidwright.design.Cell extends Object implements Serializable
  
  serialVersionUID:
  
  -7306962281439099435L
  - Serialized Fields
    - name
```
String name
```
      Name of the cell
    - type
```
String type
```
      Library element type
    - bel
```
BEL bel
```
      The physical BEL type on which the cell is placed
    - siteInst
```
SiteInst siteInst
```
      The specific site instance to which this cell corresponds
    - edifHierCellInst
```
EDIFHierCellInst edifHierCellInst
```
      The actual logical netlist cell
    - pinMappingsP2L
```
Map<K,V> pinMappingsP2L
```
      A mapping of the physical to logical cell pin names
    - pinMappingsL2P
```
Map<K,V> pinMappingsL2P
```
      A mapping of the logical to physical cell pin names
    - altPinMappingsP2L
```
Map<K,V> altPinMappingsP2L
```
      Instance data for RouteThru Cells with multiple P2L pin mappings.
    - fixedPins
```
HashSet<E> fixedPins
```
      The set of pins that are marked fixed
    - flags
```
int flags
```
      Various flags stored as bits
- Class com.xilinx.rapidwright.design.Design extends Object implements Serializable
  
  serialVersionUID:
  
  759313754786828741L
  - Serialized Fields
    - name
```
String name
```
      Name of the design
    - part
```
Part part
```
      This is the Xilinx part, package and speed grade that this design targets
    - modules
```
HashMap<K,V> modules
```
      This is the list of modules or macros in the design
    - moduleInsts
```
HashMap<K,V> moduleInsts
```
      Keeps track of module instances and groups them according to module instance name
    - instances
```
HashMap<K,V> instances
```
      This is a list of all the instances of sites and macros in the design
    - usedSites
```
Map<K,V> usedSites
```
      A map used to keep track of all used sites used by the design
    - nets
```
HashMap<K,V> nets
```
      This is a list of all the nets in the design
    - cells
```
HashMap<K,V> cells
```
      Map of all cells in the design
    - netlist
```
EDIFNetlist netlist
```
      Reference to the logical netlist
    - nocDesign
```
NOCDesign nocDesign
```
      Reference to the NOC design
    - designHeader
```
DesignHeader designHeader
```
      Used for reading and writing DCP files
    - dcpAttributes
```
HashMap<K,V> dcpAttributes
```
      Store attributes that go into the DCP XML file
    - dcpMultiAttributes
```
Map<K,V> dcpMultiAttributes
```
      Stores attributes that contain multiple values
    - cellInstMap
```
HashMap<K,V> cellInstMap
```
    - netMap
```
HashMap<K,V> netMap
```
    - xdcConstraints
```
HashMap<K,V> xdcConstraints
```
    - partitionPins
```
List<E> partitionPins
```
    - oocModules
```
List<E> oocModules
```
    - routePartitions
```
List<E> routePartitions
```
    - clockPortPartitions
```
List<E> clockPortPartitions
```
    - clockRoutingPartitions
```
List<E> clockRoutingPartitions
```
    - pulsedLatches
```
Map<K,V> pulsedLatches
```
    - trackSiteInstChanges
```
boolean trackSiteInstChanges
```
    - trackNetChanges
```
boolean trackNetChanges
```
    - modifiedSiteInsts
```
Set<E> modifiedSiteInsts
```
    - modifiedNets
```
Set<E> modifiedNets
```
    - copyOrigNets
```
boolean copyOrigNets
```
    - copyOrigSiteInsts
```
boolean copyOrigSiteInsts
```
    - origSiteInsts
```
Map<K,V> origSiteInsts
```
    - origNets
```
Map<K,V> origNets
```
    - manuallyRoutedSites
```
Set<E> manuallyRoutedSites
```
    - belAttrs
```
Map<K,V> belAttrs
```
    - aiedb
```
byte[] aiedb
```
    - memImageDB
```
byte[] memImageDB
```
    - binaryNetlist
```
byte[] binaryNetlist
```
    - binaryConstraints
```
byte[] binaryConstraints
```
    - binaryTimingGraph
```
byte[] binaryTimingGraph
```
    - hwDef
```
byte[] hwDef
```
    - boundarySites
```
byte[] boundarySites
```
    - instWithHierSepMap
```
Map<K,V> instWithHierSepMap
```
    - netsWithHierSepMap
```
Map<K,V> netsWithHierSepMap
```
    - write2024Dot1DCP
```
boolean write2024Dot1DCP
```
- Class com.xilinx.rapidwright.design.Module extends Object implements Serializable
  
  serialVersionUID:
  
  7127893920489370872L
  - Serialized Fields
    - dev
```
Device dev
```
      The device this module maps to
    - name
```
String name
```
      Unique name of this module
    - anchor
```
Site anchor
```
      This is the anchor instance of the module
    - implementationIndex
```
int implementationIndex
```
      A module contains an implementation of a type of module. All modules with the same name can have different implementations The implementationIndex enumerates all the present implementations for a given design
    - portMap
```
HashMap<K,V> portMap
```
      Ports on the module
    - instanceMap
```
HashMap<K,V> instanceMap
```
      Instances which are part of the module
    - netMap
```
HashMap<K,V> netMap
```
      Nets of the module
    - minClkPeriod
```
float minClkPeriod
```
      Keeps track of the minimum clock period of this module
    - metaDataMap
```
HashMap<K,V> metaDataMap
```
      Provides a catch-all map to store information about hard macro
    - pblock
```
PBlock pblock
```
      The PBlock used when creating this module
    - cells
```
HashMap<K,V> cells
```
      Map of all cells in the module
    - siteMap
```
HashMap<K,V> siteMap
```
    - validPlacements
```
ArrayList<E> validPlacements
```
    - netlist
```
EDIFNetlist netlist
```
    - clocks
```
HashMap<K,V> clocks
```
    - srcDatFile
```
String srcDatFile
```
    - nocDesign
```
NOCDesign nocDesign
```
    - boundingBox
```
RelocatableTileRectangle boundingBox
```
    - routingSLRSpan
```
Integer routingSLRSpan
```
- Class com.xilinx.rapidwright.design.ModuleImpls extends ArrayList<Module> implements Serializable
  
  serialVersionUID:
  
  -8931048535637180230L
  - Serialized Fields
    - allPlacements
```
List<E> allPlacements
```
- Class com.xilinx.rapidwright.design.Net extends Object implements Serializable
  
  serialVersionUID:
  
  6252168375875946963L
  - Serialized Fields
    - name
```
String name
```
      Unique name of the net
    - sitePinInsts
```
List<E> sitePinInsts
```
      Source and sink pins of the net
    - pips
```
List<E> pips
```
      Routing resources or Programmable-Interconnect-Points
    - source
```
SitePinInst source
```
      The source pin for the net
    - alternateSource
```
SitePinInst alternateSource
```
      An alternate source pin for the net (for dual output scenarios)
    - moduleInst
```
ModuleInst moduleInst
```
      The module instance this net is a member of
    - moduleTemplate
```
Module moduleTemplate
```
      The module template (or definition) this net is a member of
    - moduleTemplateNet
```
Net moduleTemplateNet
```
      The net in the module template corresponding to this net
    - logicalHierNet
```
EDIFHierNet logicalHierNet
```
      Reference to logical hierarchical net
    - cTags
```
Set<E> cTags
```
      Which sites have ctags connections to this net
    - design
```
Design design
```
      Reference to the design to which this net belongs
    - hasGapRoutingTypeFanOut
```
int hasGapRoutingTypeFanOut
```
      A packed integer that represents [31] = hasGapRouting: Flag indicating if a net has gap routing, mostly associated with clock plan routing post place, pre-routing [30-29] = NetType.ordinal(): Type of net (VCC, GND, WIRE) [28-0] = fanOut: the number of site pin sinks
- Class com.xilinx.rapidwright.design.Port extends Object implements Serializable
  
  serialVersionUID:
  
  -8961782654770650827L
  - Serialized Fields
    - name
```
String name
```
      Name of the Port of the current module, this is the port of an instance in the module.
    - sitePinInsts
```
Set<E> sitePinInsts
```
      This is the pin that the port references.
    - type
```
PortType type
```
      Port type (provided by metadata)
    - passThruPortNames
```
ArrayList<E> passThruPortNames
```
      List of port names this port connects directly to (pass-thru connections)
    - partitionPinLoc
```
Tile partitionPinLoc
```
      Specifies the tile where the partition pin should go
    - isOutputPort
```
boolean isOutputPort
```
      Flag to be used when no pin is available denoting direction of port
    - worstCasePortDelay
```
float worstCasePortDelay
```
      Worst case delay in or out of the port in nanoseconds
    - boundingBox
```
RelocatableTileRectangle boundingBox
```
- Class com.xilinx.rapidwright.design.SiteInst extends Object implements Serializable
  
  serialVersionUID:
  
  -7993281723620318536L
  - Serialized Fields
    - name
```
String name
```
      Unique name of this instance
    - type
```
SiteTypeEnum type
```
      Type of the instance (e.g. "SLICEM" or "SLICEL")
    - site
```
Site site
```
      This is a site of where the instance will reside
    - pinMap
```
HashMap<K,V> pinMap
```
      A list of all pins on this instance which are connected in nets
    - moduleInst
```
ModuleInst moduleInst
```
      Name of the module instance which this instance belongs to
    - moduleTemplate
```
Module moduleTemplate
```
      The module template (or definition) this instance is a member of
    - moduleTemplateInst
```
SiteInst moduleTemplateInst
```
      The instance in the module template corresponding to this instance
    - cells
```
HashMap<K,V> cells
```
      VIVADO ADDITION - keep track of cells by placed bel name
    - isSiteLocked
```
boolean isSiteLocked
```
      VIVADO ADDITION - locked flag for site
    - sitePIPs
```
byte[] sitePIPs
```
      Compact array, each byte represents state of a site PIP from the site type
    - siteCTags
```
HashMap<K,V> siteCTags
```
      VIVADO ADDITION - Site CTags - TODO improve storage
    - cTagsToNet
```
HashMap<K,V> cTagsToNet
```
      VIVADO ADDITION - Site CTags - TODO improve storage
- Class com.xilinx.rapidwright.design.SitePinInst extends Object implements Serializable
  
  serialVersionUID:
  
  -6675131973998249758L
  - Serialized Fields
    - pinType
```
PinType pinType
```
      The type of pin (directionality), in/out/inout
    - name
```
String name
```
      The internal pin name on the instance this pin refers to
    - siteInst
```
SiteInst siteInst
```
      The site instance where the pin is located
    - port
```
Port port
```
      The Port that references this pin, if there is one
    - net
```
Net net
```
      The net this pin is a member of
    - isRouted
```
boolean isRouted
```
      If this is an inpin (sink), it indicates there exists routing from source to this sink. If this is a source pin it is true only if all sink pins are fully routed.
Package com.xilinx.rapidwright.design.blocks
- Class com.xilinx.rapidwright.design.blocks.PBlock extends ArrayList<PBlockRange> implements Serializable
  
  serialVersionUID:
  
  -8009759451075978785L
  - Serialized Fields
    - subPBlocks
```
ArrayList<E> subPBlocks
```
    - tileSet
```
Set<E> tileSet
```
    - name
```
String name
```
    - parent
```
PBlock parent
```
    - containRouting
```
boolean containRouting
```
- Class com.xilinx.rapidwright.design.blocks.SubPBlock extends PBlock implements Serializable
  
  serialVersionUID:
  
  -5272887799353790281L
  - Serialized Fields
    - getCellsArgs
```
String getCellsArgs
```
Package com.xilinx.rapidwright.device
- Class com.xilinx.rapidwright.device.ClockRegion extends Object implements Serializable
  
  serialVersionUID:
  
  -4207323451319528717L
  - Serialized Fields
    - row
```
int row
```
      The row (or clock region Y coordinate)
    - column
```
int column
```
      The column (or clock region X coordinate)
    - name
```
String name
```
      The name of the clock region (X#Y#)
    - upperLeft
```
Tile upperLeft
```
      The upper left most tile within the clock region
    - lowerRight
```
Tile lowerRight
```
      The lower right most tile within the clock region
    - configRowIndex
```
int configRowIndex
```
      The configuration row index (ordering) for bitstream configuration
    - slr
```
SLR slr
```
      The SLR this clock regions belongs to
- Class com.xilinx.rapidwright.device.Device extends Object implements Serializable
  
  serialVersionUID:
  
  6336619462392618775L
  - Serialized Fields
    - hasModularSLRs
```
boolean hasModularSLRs
```
    - rows
```
int rows
```
      Number of rows of tiles in the device
    - columns
```
int columns
```
      Number of columns of tiles in the device
    - tiles
```
Tile[][] tiles
```
      A 2D array of all the tiles in the device
    - deviceName
```
String deviceName
```
      The Xilinx part name of the device, ie. xcku040, omits package and speed grade, but includes revision (-es1, -es2, ...)
    - sites
```
Map<K,V> sites
```
      Keeps track of all the site instances on the device
    - tileMap
```
Map<K,V> tileMap
```
      A Map between a tile name (string) and its actual reference
    - tileTypes
```
TileType[] tileTypes
```
      Array of all tile types
    - tileTypeObjMap
```
Map<K,V> tileTypeObjMap
```
      Convenience map to get tile type objects by type name
    - tilePatterns
```
TilePattern[] tilePatterns
```
      Array of all tile patterns
    - nodeTemplates
```
NodeTemplates nodeTemplates
```
      Storage of all the node templates for the device
    - siteTypes
```
SiteType[] siteTypes
```
      Array of all site types
    - siteTypeObjMap
```
Map<K,V> siteTypeObjMap
```
      Convenience map to get site type objects by type name
    - costCodeNames
```
String[] costCodeNames
```
      Array of cost code names where the index is the code
    - costCodeMap
```
Map<K,V> costCodeMap
```
      Convenience map to get cost codes from name
    - clockRegions
```
ClockRegion[][] clockRegions
```
      Clock regions on the device
    - slrs
```
SLR[] slrs
```
      SLRs on the device
    - tileToCRMap
```
Map<K,V> tileToCRMap
```
      Lazily built map to provide a mapping between tiles and clock regions
    - packages
```
HashMap<K,V> packages
```
      Map to all supported package information compatible with device
    - isDerivedDie
```
boolean isDerivedDie
```
      Flag indicating if device is a derived die
    - masterSLRIndex
```
int masterSLRIndex
```
    - configOrderIndexMap
```
Map<K,V> configOrderIndexMap
```
    - siteToIndex
```
Map<K,V> siteToIndex
```
      Enumerates all sites with a unique index
    - indexedSites
```
Site[] indexedSites
```
      Array of all sites ordered by index
    - siteBELStartIndices
```
long[] siteBELStartIndices
```
      Array of global BEL indices that reference the first BEL of each site
    - series
```
Series series
```
    - siteIndex
```
ArrayList<E> siteIndex
```
      Created on demand when user calls getSiteIndex(), where the ArrayList index is the ordinal of the SiteTypeEnum
    - activePackage
```
Package activePackage
```
      Sets the package in use for the device
    - tileExamples
```
Map<K,V> tileExamples
```
    - tileByRootNameCache
```
Map<K,V> tileByRootNameCache
```
    - altTilePatterns
```
Map<K,V> altTilePatterns
```
    - altTilePatternsLock
```
Object altTilePatternsLock
```
- Class com.xilinx.rapidwright.device.PIP extends Object implements Serializable
  
  serialVersionUID:
  
  122367735864726588L
  - Serialized Fields
    - tile
```
Tile tile
```
      The tile where this PIP is located
    - flagsAndStartWire
```
int flagsAndStartWire
```
      [31:20] 12 bits for the delay index (delay arcs only) [19] = 1 bit for isClockSpecial [18] = 1 bit for isSpecialInvertingArc [17:0] 18 bits for start wire of the PIP
    - flagsAndEndWire
```
int flagsAndEndWire
```
      [31:29] = 3 MSBs are PIPType, [28] = 1 bit for isStubArc [27] = 1 bit for isDelayArc [26] = 1 bit for isLogicalDriverArc [25] = 1 bit for isGapArc [24] = 1 bit for isNullArc [23] = 1 bit for isInvertingArc [22] = 1 bit for isFixedArc [21] = 1 bit for isStartStub [20] = 1 bit for isReverse [19] = 1 bit for isBranchStart (GAP nodes only) [18] = 1 bit for isBranchEnd (GAP nodes only) [17:0] = 16 bits are the ending wire of the PIP (ex: INT_X1Y1 START_WIRE -> END_WIRE)
- Class com.xilinx.rapidwright.device.Site extends Object implements Serializable
  
  serialVersionUID:
  
  4891980590392076374L
  - Serialized Fields
    - name
```
String name
```
      Name of the primitive site with X and Y coordinates (ie. SLICE_X0Y0)
    - type
```
SiteType type
```
      The type of this site
    - flags_siteIndexInTile
```
int flags_siteIndexInTile
```
      The index of this site in the tile (or tile type)
    - tile
```
Tile tile
```
      The tile where this site resides
    - instanceIndicies
```
int instanceIndicies
```
      The X and Y coordinate of the instance (ex: SLICE_X#Y#)
    - rpmCoordinates
```
int rpmCoordinates
```
      The RPM X and Y coordinates
    - slrIndex
```
int slrIndex
```
      Titan: Named SLR index
- Class com.xilinx.rapidwright.device.Tile extends Object implements Serializable
  
  serialVersionUID:
  
  2470255220468954877L
  - Serialized Fields
    - name
```
String name
```
      Name of the tile
    - type
```
TileType type
```
      Tile Type (INT,CLB,...)
    - sites
```
Site[] sites
```
      An array of sites located within the tile (null if none)
    - row
```
int row
```
      Absolute tile row number - the index into the device Tiles[][] array
    - column
```
int column
```
      Absolute tile column number - the index into the device Tiles[][] array
    - tileYCoordinate
```
int tileYCoordinate
```
      This is the Y coordinate in the tile name (ex: 5 in INT_X0Y5)
    - rootName
```
String rootName
```
      This is the start of the name without any _X?Y? suffix
    - tileXCoordinate
```
int tileXCoordinate
```
      This is the X coordinate in the tile name (ex: 0 in INT_X0Y5)
    - tilePatternIndex
```
int tilePatternIndex
```
      The index of the tile pattern object corresponding to this tile
    - dev
```
Device dev
```
      Reference to this tile's device object
    - uniqueWireStartIndex
```
int uniqueWireStartIndex
```
      The global start index for this tile when numbering every wire in the part
    - slrIndex
```
int slrIndex
```
      Titan: Named SLR index
Package com.xilinx.rapidwright.device.helper
- Class com.xilinx.rapidwright.device.helper.HashPool extends HashMap<Integer,ArrayList<E>> implements Serializable
  
  serialVersionUID:
  
  -7643508400771696765L
  - Serialized Fields
    - enumerations
```
ArrayList<E> enumerations
```
    - enumerationMap
```
HashMap<K,V> enumerationMap
```
- Class com.xilinx.rapidwright.device.helper.TileColumnPattern extends ArrayList<TileTypeEnum> implements Serializable
  
  serialVersionUID:
  
  3453628493683591805L
  - Serialized Fields
    - flags
```
EnumSet<E extends Enum<E>> flags
```
      Packs a number of has___() flags for quick answers
    - numInstances
```
int numInstances
```
      Place holder for the number of occurrences of this tile column pattern in a particular device
- Class com.xilinx.rapidwright.device.helper.TileSources extends Object implements Serializable
  
  serialVersionUID:
  
  -139462627137160891L
  - Serialized Fields
    - sources
```
int[] sources
```
      Sources of the tile
Package com.xilinx.rapidwright.edif
- Class com.xilinx.rapidwright.edif.EDIFParseException extends RuntimeException implements Serializable
- Class com.xilinx.rapidwright.edif.EDIFPortInstList extends ArrayList<EDIFPortInst> implements Serializable
  
  serialVersionUID:
  
  8718591209309655922L
- Class com.xilinx.rapidwright.edif.TokenTooLongException extends EDIFParseException implements Serializable
Package com.xilinx.rapidwright.interchange
- Class com.xilinx.rapidwright.interchange.IdentityEnumerator extends ArrayList<T> implements Serializable
  
  serialVersionUID:
  
  5235125492429382642L
  - Serialized Fields
    - map
```
Map<K,V> map
```
- Class com.xilinx.rapidwright.interchange.LongEnumerator extends ArrayList<Long> implements Serializable
  
  serialVersionUID:
  
  5235125492429382642L
  - Serialized Fields
    - map
```
HashMap<K,V> map
```
- Class com.xilinx.rapidwright.interchange.StringEnumerator extends ArrayList<String> implements Serializable
  
  serialVersionUID:
  
  5235125492429382642L
  - Serialized Fields
    - map
```
Map<K,V> map
```
Package com.xilinx.rapidwright.timing
- Class com.xilinx.rapidwright.timing.TimingEdge extends org.jgrapht.graph.DefaultEdge implements Serializable
  
  serialVersionUID:
  
  5888111557223514042L
  - Serialized Fields
    - hasEDIFPortInsts
```
boolean hasEDIFPortInsts
```
    - srcPort
```
EDIFPortInst srcPort
```
    - dstPort
```
EDIFPortInst dstPort
```
    - timingGraph
```
TimingGraph timingGraph
```
    - net
```
Net net
```
    - edifNet
```
EDIFNet edifNet
```
    - src
```
TimingVertex src
```
    - dst
```
TimingVertex dst
```
    - logicDelay
```
float logicDelay
```
    - netDelay
```
float netDelay
```
    - delay
```
float delay
```
    - intraSiteDelay
```
float intraSiteDelay
```
      Added for delay update of a timing edge, because intra-site delay does not change during routing and needs to be stored separately
    - first
```
SitePinInst first
```
    - second
```
SitePinInst second
```
- Class com.xilinx.rapidwright.timing.TimingGraph extends org.jgrapht.graph.DefaultDirectedWeightedGraph<TimingVertex,TimingEdge> implements Serializable
  
  serialVersionUID:
  
  7072333598844760465L
  - Serialized Fields
    - debug
```
boolean debug
```
    - verbose
```
boolean verbose
```
    - timingModel
```
TimingModel timingModel
```
    - timingManager
```
TimingManager timingManager
```
    - graphPathHashSet
```
HashSet<E> graphPathHashSet
```
    - hierCellInstMap
```
HashMap<K,V> hierCellInstMap
```
    - intrasiteAndLogicDelayModel
```
DelayModel intrasiteAndLogicDelayModel
```
    - graphVizPrintStream
```
PrintStream graphVizPrintStream
```
    - myCellMap
```
HashMap<K,V> myCellMap
```
    - design
```
Design design
```
    - set
```
ArrayList<E> set
```
    - safeVertexCheck
```
HashMap<K,V> safeVertexCheck
```
    - timingEdgeConnectionMap
```
Map<K,V> timingEdgeConnectionMap
```
      A map from TimingEdges to connections
    - sinkSitePinInstTimingEdges
```
Map<K,V> sinkSitePinInstTimingEdges
```
      Mapping between each sink SitePinInst instance and its associated TimingEdge instances
    - edifHPortMap
```
Map<K,V> edifHPortMap
```
      Mapping between a logic pin and a physical pin recognized by the timing graph builder
    - orderedTimingVertices
```
List<E> orderedTimingVertices
```
    - reversedOrderedTimingVertices
```
List<E> reversedOrderedTimingVertices
```
    - clkRouteTiming
```
ClkRouteTiming clkRouteTiming
```
    - routerTimer
```
RuntimeTrackerTree routerTimer
```
    - dspTimingDataFolder
```
String dspTimingDataFolder
```
      DSP timing data related variables
    - dspTimingDataFolderWarning
```
boolean dspTimingDataFolderWarning
```
    - dspTimingFileExistenceWarning
```
boolean dspTimingFileExistenceWarning
```
    - dspNameDataMapping
```
Map<K,V> dspNameDataMapping
```
    - dspTimingDataSet
```
Set<E> dspTimingDataSet
```
    - superSource
```
TimingVertex superSource
```
      The superSource and superSink are used to consolidate all timing start and end points, respectively. They simplify timing computations and data to compute clock skew will be annotated on the edges from superSource and to superSink. For example, a FF will be represented both as a start and end points using two vertices, says source and sink. The superSource will have no input, but fanout to all the start points nodes. The superSink will have fanin from all the end point nodes and have no output.
    - superSink
```
TimingVertex superSink
```
    - srcCell
```
Cell srcCell
```
    - dstCell
```
Cell dstCell
```
    - source
```
BELPin source
```
    - sink
```
BELPin sink
```
    - si
```
SiteInst si
```
    - intraSiteDelay
```
float intraSiteDelay
```
    - overwriteBUGCEDelay
```
boolean overwriteBUGCEDelay
```
Package com.xilinx.rapidwright.timing.delayestimator
- Class com.xilinx.rapidwright.timing.delayestimator.DelayEstimatorBase extends Object implements Serializable
  - Serialized Fields
    - distArrays
```
Map<K,V> distArrays
```
    - numCol
```
int numCol
```
    - numRow
```
int numRow
```
    - K0
```
Map<K,V> K0
```
    - K1
```
Map<K,V> K1
```
    - K2
```
Map<K,V> K2
```
    - L
```
Map<K,V> L
```
    - inputSitePinDelay
```
Map<K,V> inputSitePinDelay
```
    - ictInfo
```
InterconnectInfo ictInfo
```
    - verbose
```
int verbose
```
    - useUTurnNodes
```
boolean useUTurnNodes
```
- Class com.xilinx.rapidwright.timing.delayestimator.InterconnectInfo extends Object implements Serializable

Serialized Form

Package com.xilinx.rapidwright.design

Class com.xilinx.rapidwright.design.Cell extends Object implements Serializable

Serialized Fields

name

type

bel

siteInst

edifHierCellInst

pinMappingsP2L

pinMappingsL2P

altPinMappingsP2L

fixedPins

flags

Class com.xilinx.rapidwright.design.Design extends Object implements Serializable

Serialized Fields

name

part

modules

moduleInsts

instances

usedSites

nets

cells

netlist

nocDesign

designHeader

dcpAttributes

dcpMultiAttributes

cellInstMap

netMap

xdcConstraints

partitionPins

oocModules

routePartitions

clockPortPartitions

clockRoutingPartitions

pulsedLatches

trackSiteInstChanges

trackNetChanges

modifiedSiteInsts

modifiedNets

copyOrigNets

copyOrigSiteInsts

origSiteInsts

origNets

manuallyRoutedSites

belAttrs

aiedb

memImageDB

binaryNetlist

binaryConstraints

binaryTimingGraph

hwDef

boundarySites

instWithHierSepMap

netsWithHierSepMap

write2024Dot1DCP

Class com.xilinx.rapidwright.design.Module extends Object implements Serializable

Serialized Fields

dev

name

anchor

implementationIndex

portMap

instanceMap

netMap

minClkPeriod

metaDataMap

pblock

cells

siteMap

validPlacements

netlist

clocks

srcDatFile

nocDesign

boundingBox

routingSLRSpan

Class com.xilinx.rapidwright.design.ModuleImpls extends ArrayList<Module> implements Serializable