com.xilinx.rapidwright.examples

Class SLRCrosserGenerator

Object

com.xilinx.rapidwright.examples.SLRCrosserGenerator

public class SLRCrosserGenerator
extends Object

Highly parameterizable SLR bridge crossing circuit generator for UltraScale+ devices. Will write out a placed and routed DCP with SLR crossings already realized. Created on: Jan 31, 2018

Field Summary

Fields

Modifier and Type	Field and Description
static int	LAGUNA_FLOPS_PER_SITE
static int	LAGUNA_SITES_PER_TILE
static int	LAGUNA_TILES_PER_FSR

Constructor Summary

Constructors

Constructor and Description
SLRCrosserGenerator()

Method Summary

Modifier and Type	Method and Description
static void	createBUFGCE(Design d, String clkName, String clkInName, String clkOutName, String bufgceInstName) Creates/instantiates a BUFGCE in the design
static void	createBUFGCEAndFlops(Design d, int northBusWidth, int southBusWidth, List<String> busPrefixes, String clkName, String clkInName, String clkOutName, String bufgceInstName) Creates the logical netlist of the SLR crosser design.
static void	customRouteSLRCrossingClock(Design d, String clkName, String[] lagunaStarts, String txClkWire, String rxClkWire, boolean useCommonCentroid)
static ClockRegion	findCentroid(String[] lagunaStarts, Device dev)
static Map<RouteNode,List<SitePinInst>>	getLCBPinMappings(Net clk, String txClkWire, String rxClkWire) Separates clock sinks by direction in a half clock region so they can be driven by independent leaf clock buffers (LCBs).
static void	main(String[] args)
static Net	placeAndRouteLagunaFlopPair(Design d, EDIFHierNet path, Site txSite, String txElementName) Given a logical net and site/bel site, this method will perform the placement and routing of two laguna flops and their inter-site super-long-line routing.
static void	placeAndRouteSLRCrossing(Design d, Site northStart, String northBusName, String southBusName, int northBusWidth, int southBusWidth) Places and routes an SLR crossing given a north and south bus of size width.
static Cell	placeBUFGCE(Design d, Site s, String bufName) Places a BUFGCE present in the netlist.
static void	routeControlSignalsInLagunaSite(Cell c, Net clk, Net rst, Net ce) Routes the control signals (CLK,CE,RST) for a laguna flop within its site.
static SitePin	routeToLagunaRx(Net n) Routes the current incomplete net to its corresponding RX site.

Methods inherited from class Object

equals, getClass, hashCode, notify, notifyAll, toString, wait, wait, wait

Field Detail

LAGUNA_FLOPS_PER_SITE

public static final int LAGUNA_FLOPS_PER_SITE

See Also:

Constant Field Values

LAGUNA_SITES_PER_TILE

public static final int LAGUNA_SITES_PER_TILE

See Also:

Constant Field Values

LAGUNA_TILES_PER_FSR

public static final int LAGUNA_TILES_PER_FSR

See Also:

Constant Field Values

Constructor Detail

SLRCrosserGenerator

public SLRCrosserGenerator()

Method Detail

routeToLagunaRx

public static SitePin routeToLagunaRx(Net n)

Routes the current incomplete net to its corresponding RX site. It will add the necessary PIPs to the net to route it, but will not add the site pin.

Parameters:

n - The net with a Laguna TX pin source.

Returns:

The RX site pin.

routeControlSignalsInLagunaSite

public static void routeControlSignalsInLagunaSite(Cell c,
                                                   Net clk,
                                                   Net rst,
                                                   Net ce)

Routes the control signals (CLK,CE,RST) for a laguna flop within its site.

Parameters:

c - The laguna flop cell to route signals to

clk - The physical clock net to route

rst - The physical reset net to route

ce - The physical ce net to route

placeAndRouteLagunaFlopPair

public static Net placeAndRouteLagunaFlopPair(Design d,
                                              EDIFHierNet path,
                                              Site txSite,
                                              String txElementName)

Given a logical net and site/bel site, this method will perform the placement and routing of two laguna flops and their inter-site super-long-line routing.

Parameters:

d - The current design.

path - The logical net to implement as an SLR crossing signal

txSite - The laguna site onto which to place the TX flop

txElementName - The element/bel site to place the TX flop

Returns:

The physical net routed across the super long line

placeBUFGCE

public static Cell placeBUFGCE(Design d,
                               Site s,
                               String bufName)

Places a BUFGCE present in the netlist.

Parameters:

d - Design containing BUFGCE

s - Site onto which to place the BUFGCE

bufName - Full hierarchical instance name of the BUFGCE

placeAndRouteSLRCrossing

public static void placeAndRouteSLRCrossing(Design d,
                                            Site northStart,
                                            String northBusName,
                                            String southBusName,
                                            int northBusWidth,
                                            int southBusWidth)

Places and routes an SLR crossing given a north and south bus of size width.

Parameters:

d - The current design

northStart - The starting Laguna site to start placement (placement moves north) for the north traveling bus

northBusName - Full hierarchical net name of the bus to cross SLR in north direction

southBusName - Full hierarchical net name of the bus to cross SLR in south direction

northBusWidth - Width of north buses crossing SLR

southBusWidth - Width of south buses crossing SLR

getLCBPinMappings

public static Map<RouteNode,List<SitePinInst>> getLCBPinMappings(Net clk,
                                                                 String txClkWire,
                                                                 String rxClkWire)

Separates clock sinks by direction in a half clock region so they can be driven by independent leaf clock buffers (LCBs).

Parameters:

clk - The physical clock net

txClkWire - The INT tile wire name to use for TX-based clocks

rxClkWire - The INT tile wire name to use for RX-based clocks

Returns:

A map from LCB node to a list of all clk sinks to be driven by the LCB.

findCentroid

public static ClockRegion findCentroid(String[] lagunaStarts,
                                       Device dev)

customRouteSLRCrossingClock

public static void customRouteSLRCrossingClock(Design d,
                                               String clkName,
                                               String[] lagunaStarts,
                                               String txClkWire,
                                               String rxClkWire,
                                               boolean useCommonCentroid)

createBUFGCE

public static void createBUFGCE(Design d,
                                String clkName,
                                String clkInName,
                                String clkOutName,
                                String bufgceInstName)

Creates/instantiates a BUFGCE in the design

Parameters:

d - The current design

clkName - Name of the clock net

clkInName - Name of the clock in port

clkOutName - Name of the clock out port, or null for none

bufgceInstName - Name of the BUFGCE instance

createBUFGCEAndFlops

public static void createBUFGCEAndFlops(Design d,
                                        int northBusWidth,
                                        int southBusWidth,
                                        List<String> busPrefixes,
                                        String clkName,
                                        String clkInName,
                                        String clkOutName,
                                        String bufgceInstName)

Creates the logical netlist of the SLR crosser design.

Parameters:

d - Current design

northBusWidth - Width of the North buses to create

southBusWidth - Width of the South buses to create

busPrefixes - Prefixes to use for bus names

clkName - Name of the clock net

clkInName - Name of the clock in port

clkOutName - Name of the clock out port

bufgceInstName - Name of the BUFGCE instance

main

public static void main(String[] args)