RapidWright Documentation

• Introduction
  • What is RapidWright?
  • Why RapidWright?
  • What about RapidSmith?
  • Vivado and RapidWright
• Getting Started
• FPGA Architecture Basics
  • What is an FPGA?
  • CPU vs. FPGA
  • Lookup Tables (LUTs)
  • State Elements
  • Carry Chains
  • DSP Blocks
  • Block RAMs
• Xilinx Architecture Terminology
  • BEL (Basic Element of Logic)
  • Site
  • Tile
  • FSR (Fabric Sub Region or Clock Region)
  • SLR (Super Logic Region)
  • Device
• RapidWright Overview
  • Device Package
  • EDIF Package (Logical Netlist)
  • Design Package (Physical Netlist)
• Design Checkpoints
  • What is a Design Checkpoint?
  • What is Inside a Design Checkpoint?
  • RapidWright and Design Checkpoint Files
• Implementation Basics
  • Placement
  • Routing
• Merging Designs
  • Customizing Merge Behavior
• Bitstream Manipulation
  • Disclaimer
  • Overview
  • Bitstream Packet Model
  • Configuration Array Model
  • Example Usages: Modify User State Bits
  • Example Usages: Find and Print the Frames of a Placed Cell
• FPGA Interchange Format
  • What is the FPGA Interchange Format?
  • What does the FPGA Interchange Format enable?
  • How is RapidWright related to the FPGA Interchange Format?
  • Additional Resources
• RapidWright Publications
  • Original RapidWright Publication - FCCM 2018
  • Additional RapidWright Publications
  • Community Competitions
  • Select Community Publications
• A Pre-implemented Module Flow
  • Background and Flow Comparison
  • High Performance Flow
  • Rapid Prototyping Flow
• RapidWright Tutorials
  • RWRoute Timing-driven Routing
  • RWRoute Wirelength-driven Routing
  • RWRoute Partial Routing
  • RapidWright Report Timing Example
  • Reuse Timing-closed Logic As A Shell
  • Use DREAMPlaceFPGA to Place a Netlist via FPGA Interchange Format
  • Polynomial Generator: Placed and Routed Circuits in Seconds
  • Inserting and Routing a Debug Core As An ECO
  • Create Placed and Routed DCP to Cross SLR
  • Build an IP Integrator Design with Pre-Implemented Blocks
  • RapidWright PipelineGenerator Example
  • RapidWright PipelineGeneratorWithRouting Example
  • Pre-implemented Modules - Part I
  • Pre-implemented Modules - Part II
  • Create and Use an SLR Bridge
  • RapidWright FPGA 2019 Deep Dive Tutorial
  • RapidWright FCCM 2019 Workshop
  • RapidWright FPL 2019 Tutorial
  • RapidWright ICCAD 2023 Hands-on Tutorial
• Tech Articles
  • Call RapidWright from C/C++ Using GraalVM
  • Using RapidWright Directly in Python 3
  • Setup JUnit 5 Tests in RapidWright
  • RapidWright Data Files
• Frequently Asked Questions
  • I can’t open my DCP in RapidWright, I get ‘ERROR: Couldn’t determine a proper EDIF netlist to load with the DCP file …’, what should I do?
  • Can RapidWright be used for designs targeting the AWS F1 platform?
  • When should I use RapidWright and when should I use Vivado?
  • What languages does RapidWright support, and how do I interact with them?
  • Why is the framework called RapidWright?
  • Can RapidWright generate bitstreams?
  • Does RapidWright provide device timing information?
  • Does RapidWright support partial reconfiguration (PR)?
  • Is there any published work on RapidWright?
• Glossary