RWRoute Wirelength-driven Routing¶
Routes an example design (e.g. “gnl_2_4_7_3.0_gnl_3500_03_7_80_80.dcp”).
This example shows how to use RWRoute in the faster, wirelength-driven mode and validate routing results with Vivado.
Steps to Run¶
Download the example
gnl_2_4_7_3.0_gnl_3500_03_7_80_80.dcpdesign:
wget http://www.rapidwright.io/docs/_downloads/gnl_2_4_7_3.0_gnl_3500_03_7_80_80.dcp
Invoke RWRoute via gradle (this will ensure code is compiled before running):
rapidwright RWRoute gnl_2_4_7_3.0_gnl_3500_03_7_80_80.dcp gnl_2_4_7_3.0_gnl_3500_03_7_80_80_routed.dcp --nonTimingDriven
Please refer to the documentation Javadoc and code for more implementation details. The Java source code for RWRoute is located in: RapidWright/src/com/xilinx/rapidwright/rwroute/.
Example Output¶
Example output using the gnl_2_4_7_3.0_gnl_3500_03_7_80_80.dcp design is included below:
==============================================================================
== RWRoute ==
==============================================================================
==============================================================================
== Reading DCP: gnl_2_4_7_3.0_gnl_3500_03_7_80_80.dcp ==
==============================================================================
XML Parse & Device Load: 2.293s
EDIF Parse: 2.078s
Read XDEF Header: 0.054s
Read XDEF Caches: 0.060s
Read XDEF Placement: 0.511s
Read XDEF Routing: 0.100s
------------------------------------------------------------------------------
[No GC] *Total*: 5.097s
==============================================================================
== Route Design ==
==============================================================================
INFO: Route 2123 pins of GLOBAL_LOGIC1
------------------------------------------------------------------------------
Generated RRG Routed Nodes With Total Run
Iteration RRG Nodes Time (s) Connections Overlaps Time (s)
--------- ---------------------- ----------- ---------- ----------------
1 226748 0.94 14952 3847 1.83
2 11743 0.08 7082 2483 0.58
3 15013 0.10 5378 1343 0.70
4 18160 0.13 3235 566 0.73
5 17743 0.13 1411 106 0.53
6 5002 0.04 328 7 0.40
7 1654 0.01 30 0 0.06
------------------------------------------------------------------------------
INFO: Route 0 direct connections
INFO: No PIP overlaps
==============================================================================
== Statistics ==
==============================================================================
Total wirelength: 12309
Route design: 5.57s
├─ Initialization: 0.25s
└─ Routing: 5.32s
==============================================================================
Write EDIF: 0.128s
Writing XDEF Header: 0.169s
Writing XDEF Placement: 0.464s
Writing XDEF Routing: 0.614s
Writing XDEF Finalizing: 0.051s
Writing XDC: 0.007s
------------------------------------------------------------------------------
[No GC] *Total*: 1.433s
INFO: Write routed design
gnl_2_4_7_3.0_gnl_3500_03_7_80_80_routed.dcp
The output contains three main sections regarding reading the design checkpoint, RWRoute processing info, and routing statistics.
Validation with Vivado¶
To validate the routed design by Vivado, run the following at the prompt:
vivado -mode tcl gnl_2_4_7_3.0_gnl_3500_03_7_80_80_routed.dcp
and then run the following command at the Tcl prompt:
report_route_status
The design is successfully routed, as all the routable nets are fully routed and there is no nets with routing errors.
Design Route Status
: # nets :
------------------------------------------- : ----------- :
# of logical nets.......................... : 4937 :
# of nets not needing routing.......... : 1082 :
# of internally routed nets........ : 932 :
# of implicitly routed ports....... : 150 :
# of routable nets..................... : 3855 :
# of fully routed nets............. : 3855 :
# of nets with routing errors.......... : 0 :
------------------------------------------- : ----------- :